David Harris
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699a8f3ac3
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Extended maximum signature length to 1M
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2021-05-03 15:29:20 -04:00 |
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bbracker
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acd99be7f8
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-05-03 09:23:52 -04:00 |
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Katherine Parry
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9252d08b41
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fpu imperas tests run
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2021-05-01 02:18:01 +00:00 |
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bbracker
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0d62440f60
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-30 06:26:35 -04:00 |
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bbracker
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9c08ce5359
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rv32 plic test and lint fixes
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2021-04-30 06:26:31 -04:00 |
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Domenico Ottolia
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830787e3e1
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Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts
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2021-04-29 20:42:14 -04:00 |
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Domenico Ottolia
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750d276feb
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Minor improvements to scause test
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2021-04-29 16:48:07 -04:00 |
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Domenico Ottolia
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fdbd238a87
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Add machine-mode timer interrupts to mcause tests
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2021-04-29 16:39:18 -04:00 |
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Domenico Ottolia
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c9cb2f51d1
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Same but don't break sim-wally this time
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2021-04-29 15:33:27 -04:00 |
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Domenico Ottolia
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fdd4deec2f
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Add more exceptions to medeleg tests
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2021-04-29 15:32:13 -04:00 |
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ushakya22
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f139f248dc
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Working MIE timer tests
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2021-04-29 15:19:43 -04:00 |
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Domenico Ottolia
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99a927be47
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Add medeleg tests
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2021-04-29 15:02:36 -04:00 |
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Ross Thompson
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14a69c1d06
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Added the ability to exclude branch predictor.
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2021-04-26 14:27:42 -05:00 |
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Ross Thompson
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44d28dbd1c
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Icache integrated!
Merge branch 'icache-almost-working' into main
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2021-04-26 11:48:58 -05:00 |
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bbracker
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f921886451
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merge cleanup; mem init is broken
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2021-04-26 08:00:17 -04:00 |
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Ross Thompson
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9e40fb072c
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Merge branch 'tests' into icache-almost-working
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2021-04-25 21:25:36 -05:00 |
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Shriya Nadgauda
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2a5c243b0b
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adding pipeline testing
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2021-04-23 14:19:17 -04:00 |
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Ross Thompson
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c9bdaceddb
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Fixed icache for 32 bit.
Merge branch 'cache' into main
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2021-04-22 16:45:29 -05:00 |
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Thomas Fleming
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f9e071baf8
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Temporarily disable rv64 mmu test
Will restore once cache revamp is pushed
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2021-04-22 13:19:18 -04:00 |
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Domenico Ottolia
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82320033d5
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Add tests for stval and mtval
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2021-04-21 02:31:32 -04:00 |
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Domenico Ottolia
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fed42ffe19
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Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file
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2021-04-21 01:12:55 -04:00 |
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Domenico Ottolia
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d5f86fadac
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Add tests for sepc register
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2021-04-20 23:50:53 -04:00 |
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Ross Thompson
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649589ee2c
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Broken icache. Design is done. Time to debug.
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2021-04-20 19:55:49 -05:00 |
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Jarred Allen
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59b340dac9
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Merge branch 'main' into cache
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2021-04-19 00:05:23 -04:00 |
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bbracker
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11cf251378
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-04-15 21:09:27 -04:00 |
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bbracker
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195cead01c
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working GPIO interrupt demo
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2021-04-15 21:09:15 -04:00 |
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Domenico Ottolia
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b1cd107a00
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Add tests for scause and ucause
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2021-04-15 19:41:25 -04:00 |
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Domenico Ottolia
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8c4cfa5f69
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Add 32 bit privileged tests
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2021-04-15 16:55:39 -04:00 |
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Jarred Allen
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7b4b1a31ef
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Merge branch 'main' into cache
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2021-04-15 13:47:19 -04:00 |
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Thomas Fleming
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d281ecd067
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Remove imem from testbenches
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2021-04-14 20:20:34 -04:00 |
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Jarred Allen
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757b64e487
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Merge branch 'main' into cache
Conflicts:
wally-pipelined/src/cache/dmapped.sv
wally-pipelined/src/cache/line.sv
wally-pipelined/src/ifu/icache.sv
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2021-04-14 18:24:32 -04:00 |
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bbracker
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ccff1e6c99
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rv64 interrupt servicing
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2021-04-14 10:19:42 -04:00 |
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Jarred Allen
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357aed75ee
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A few more cache fixes
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2021-04-13 01:07:40 -04:00 |
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Jarred Allen
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6ce4d44ae1
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Merge from branch 'main'
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2021-04-08 17:19:34 -04:00 |
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bbracker
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0c85b1c201
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integrated peripheral testing into existing workflow
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2021-04-08 15:31:39 -04:00 |
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bbracker
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c8c87bd0d8
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merge testbench
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2021-04-08 14:28:01 -04:00 |
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Domenico Ottolia
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1bdfac6a77
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Cause an Illegal Instruction Exception when attempting to write readonly CSRs
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2021-04-08 05:12:54 -04:00 |
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Thomas Fleming
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e807f5d771
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Implement support for superpages
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2021-04-08 02:44:59 -04:00 |
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Ross Thompson
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7f12c7af90
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Switch to use RV64IC for the benchmarks.
Still not working correctly with the icache.
instr
addr correct got
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2021-04-07 19:12:43 -05:00 |
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Domenico Ottolia
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9b82fbff5a
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Add privileged tests to testbench
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2021-04-07 02:22:08 -04:00 |
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Domenico Ottolia
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bbdd4e1467
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Add passing mtval and mepc tests
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2021-04-07 02:21:05 -04:00 |
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Ross Thompson
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d901cfc848
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Merge branch 'icache_bp_bug' into tests
Not sure this merge is right.
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2021-04-06 21:46:40 -05:00 |
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Ross Thompson
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0a20e33971
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Steps to getting branch predictor benchmarks running.
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2021-04-06 21:20:51 -05:00 |
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Thomas Fleming
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8f31e00f6a
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Merge branch 'mmu' into main
Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
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2021-04-03 22:12:52 -04:00 |
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Thomas Fleming
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ac89947e98
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-04-03 22:09:50 -04:00 |
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Katherine Parry
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08b31f7b2a
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Integrated FPU
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2021-04-03 20:52:26 +00:00 |
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James E. Stine
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82cd900b65
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Put back imperas testbench until figure out why m_supported is running for rv64ic
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2021-04-02 08:19:25 -05:00 |
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James E. Stine
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9026357350
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Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
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2021-04-02 06:27:37 -05:00 |
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Thomas Fleming
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f9bf2fbc01
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Implement sfence.vma and fix tlb writing
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2021-04-01 15:55:05 -04:00 |
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Ross Thompson
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1e83810450
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Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
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2021-03-30 23:18:20 -05:00 |
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