285 Commits

Author	SHA1	Message	Date
Ross Thompson	5c16b65a16	simplified uncore's name for HWDATA.	2022-03-10 18:17:44 -06:00
Ross Thompson	543e10ab32	Moved subwordwrite to lsu directory.	2022-03-10 18:15:25 -06:00
Ross Thompson	54abd944e2	Simplified byte write enable logic.	2022-03-10 18:13:35 -06:00
Ross Thompson	50789f9ddd	Byte write enables are passing all configs now.	2022-03-10 17:26:32 -06:00
Ross Thompson	f7df3a0666	Progress on the path to getting all configs working with byte write enables.	2022-03-10 17:02:52 -06:00
Ross Thompson	83133f8c47	Partially working byte write enables. Works for cache, but not dtim or bus only.	2022-03-10 16:11:39 -06:00
Ross Thompson	d5f524a15e	Added byte write enables to cache SRAMs.	2022-03-10 15:48:31 -06:00
David Harris	b1340653cf	bit write update	2022-03-09 19:09:20 +00:00
David Harris	004853c312	Refactored SRAM bit write enable	2022-03-09 17:49:28 +00:00
David Harris	ba9320d822	Updated testbench to read expected flags	2022-03-09 13:58:17 +00:00
Ross Thompson	2a8a1cd191	Minor cleanup to interlockfsm.	2022-03-08 23:38:58 -06:00
Ross Thompson	ac9528b450	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-08 18:05:35 -06:00
Ross Thompson	ed32801cc1	Comments.	2022-03-08 18:05:25 -06:00
Ross Thompson	534fd70f76	Marked signals for name changes.	2022-03-08 17:41:02 -06:00
David Harris	5d0b9bab6e	Added more test cases and rounding modes to fma test generator	2022-03-08 23:29:29 +00:00
David Harris	cfa82efccc	fma16_testgen.c test cases	2022-03-08 23:18:18 +00:00
Ross Thompson	acd60218b8	Removed unused signal.	2022-03-08 16:58:26 -06:00
Ross Thompson	cc21414051	Added parameter to spillsupport.	2022-03-08 16:38:48 -06:00
Ross Thompson	60e6c1ffa7	Moved cacheable signal into cache.	2022-03-08 16:34:02 -06:00
David Harris	d2282d5e87	Checked in fma16_template.v	2022-03-06 13:29:35 +00:00
David Harris	48705457d5	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
David Harris	545f569f78	Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas	2022-03-03 15:38:08 +00:00
David Harris	8fbdbba81a	fma file fixes	2022-03-02 23:47:01 +00:00
bbracker	be2f668867	but apparently QEMU doesn't show UXL in SSTATUS	2022-03-02 22:44:19 +00:00
bbracker	01e0f2f0d2	update SXL UXL bits in MSTATUS to match new QEMU trace	2022-03-02 22:15:57 +00:00
David Harris	3bea7bb431	removed imperas-riscv-tests	2022-03-02 17:28:20 +00:00
David Harris	1661983345	FMA project ready to start	2022-03-01 20:58:08 +00:00
David Harris	f314e60dc8	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
David Harris	f0a7ae2bba	adrdecs comments	2022-02-28 20:33:41 +00:00
David Harris	e108eb5195	Modified address decoder for native access to CLINT	2022-02-28 19:13:14 +00:00
David Harris	3519a20ccf	hptw cleanup for synthesis	2022-02-28 05:54:34 +00:00
David Harris	bb14dba9be	Created softfloat_demo showcasing how to do math with SoftFloat	2022-02-27 18:17:21 +00:00
David Harris	c7b5d32a72	Linking against riscv-isa-sim SoftFloat library for RISC-V NaN behavior	2022-02-27 17:23:33 +00:00
David Harris	c6561d1e8b	Moved FMA back into source tree to facilitate synthesis	2022-02-27 15:41:41 +00:00
David Harris	274ecf13ad	Moved fma directory	2022-02-27 14:20:15 +00:00
David Harris	5a5142c14f	fma simulation infrastructure	2022-02-27 04:36:43 +00:00
David Harris	d917cc1379	fma passing multiply vectors	2022-02-27 04:36:01 +00:00
David Harris	8a55935456	simplified fma Makefile	2022-02-26 19:55:42 +00:00
David Harris	1852eccaab	Made softfloat.a a symlink	2022-02-26 19:53:04 +00:00
David Harris	87d1a8a1ac	Added start of fma	2022-02-26 19:51:19 +00:00
Ross Thompson	97d64201f7	Fixed bug with DAPageFault being wrong when HPTW writes not supported.	2022-02-23 10:54:34 -06:00
Ross Thompson	53f13d4cbc	More spillsupport more structual.	2022-02-23 10:27:14 -06:00
Ross Thompson	c23f6c7d90	Fixed bug with spill support and Instruction DA Page Faults.	2022-02-23 10:16:12 -06:00
Ross Thompson	62e1a97287	Added generates to pcnextf muxes for privileged and caches.	2022-02-22 22:45:00 -06:00
Ross Thompson	6a52f95cc8	Minor busdp cleanup.	2022-02-22 17:28:26 -06:00
Ross Thompson	59a2c09c5e	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-22 14:45:53 -06:00
Ross Thompson	90be3d4360	Clarified interlockfsm.	2022-02-22 11:31:28 -06:00
bbracker	b8fd06576c	fix lint bugs in PLIC and UART	2022-02-22 05:04:18 +00:00
bbracker	a6047697c3	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-22 04:27:50 +00:00
bbracker	e7934c585a	change RX side of UART to aslo be LSB-first	2022-02-22 03:34:08 +00:00