David Harris
c442dea173
Removed M sufix from busdp signals
2022-08-25 11:13:01 -07:00
David Harris
48f346baf8
Renamed LSUFunct3M to Funct3 in busdp
2022-08-25 11:08:12 -07:00
David Harris
9bada9c14a
Renaming LSU signals from busdp
2022-08-25 11:05:10 -07:00
David Harris
3ba961d1a8
renamed BusBuffer to FetchBuffer
2022-08-25 10:44:39 -07:00
David Harris
dda3b441d7
Continued busdp/ebu simplification
2022-08-25 10:20:02 -07:00
David Harris
aba914ea5e
Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
2022-08-25 09:52:08 -07:00
Ross Thompson
e605ef57dc
BROKEN. Don't use this commit.
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Issue running cacheless with bus.
2022-08-25 11:02:46 -05:00
David Harris
ae0702d129
Renamed DCache to Cache in busdp/busfsm signal interface
2022-08-25 06:21:22 -07:00
David Harris
1206b388c7
Replaced dtim with rom-based IROM in IFU. Moved cache control signals out of DTIM and IROM
2022-08-25 04:06:27 -07:00
Ross Thompson
51adf6cba9
Modified the lsu/ifu memory configurations.
2022-08-24 12:35:15 -05:00
Ross Thompson
3b07584403
Updated the names of the *WriteDataM inside the LSU to more meaningful names.
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Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
2022-08-23 10:34:39 -05:00
Ross Thompson
ebe4339953
Updated fpga test bench.
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Solved read delay cache bug. Introduced during cache optimizations.
2022-08-21 15:59:54 -05:00
Ross Thompson
2ba390adf4
Possible reduction of ignorerequest.
2022-08-19 18:07:44 -05:00
Ross Thompson
517c0f6c35
Changed signal names.
2022-08-17 16:12:04 -05:00
Ross Thompson
f6e5746e59
Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
2022-08-17 16:09:20 -05:00
Ross Thompson
57fcf0ef79
Fixed fstore2 in cache?
2022-08-01 22:04:44 -05:00
Ross Thompson
3cd8404917
Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
2022-08-01 21:08:14 -05:00
Ross Thompson
05484c4c05
signal name cleanup.
2022-07-22 23:36:27 -05:00
Katherine Parry
62205ebb3b
renamed FLoad2 to FStore2
2022-07-09 00:26:45 +00:00
Katherine Parry
97e7e619d9
moved fpu ieu write data mux to lsu
2022-07-08 23:56:57 +00:00
Madeleine Masser-Frye
ad29e19a27
fixed width mismatch for rv64 ieuadrM and readdatawordM
2022-07-06 22:39:35 +00:00
Katherine Parry
8f98f3bfab
added rv32 double precision stores - untested
2022-06-28 21:33:31 +00:00
slmnemo
be658d3933
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
2022-06-08 15:03:15 -07:00
slmnemo
a5aa75e5de
Merge branch 'main' into cacheburstmode
2022-06-08 02:21:33 +00:00
slmnemo
1d22fc707a
Added lock signal to ensure AHB speaks with the right bus
2022-06-08 02:19:21 +00:00
slmnemo
90c5e5d319
Reworked bus to handle burst interfacing
2022-06-07 11:22:53 +00:00
David Harris
129fab3794
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
2022-06-02 14:18:55 +00:00
slmnemo
efce3e4953
added LSUBurstDone signal to signal when a burst has finished
2022-05-26 16:29:13 -07:00
slmnemo
80965f953c
added burst size signals to the IFU, EBU, LSU, and busdp
2022-05-25 18:02:50 -07:00
David Harris
4c5e361b00
More unused signal cleanup
2022-05-12 15:26:08 +00:00
David Harris
5acb526375
More unused signal cleanup
2022-05-12 15:21:09 +00:00
David Harris
94459ade3d
Changed WFI to stall pipeline in memory stage
2022-05-05 02:03:44 +00:00
Kip Macsai-Goren
7bc6943527
Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
2022-04-22 22:46:11 +00:00
David Harris
a8ad7be246
Fixed WFI decoding in IFU
2022-04-18 19:02:08 +00:00
David Harris
68d9c99fba
Added WFI support to IFU to keep it in the pipeline
2022-04-14 17:26:17 +00:00
Ross Thompson
ab9738d3be
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
bbracker
54b9745a75
big interrupts refactor
2022-03-30 13:22:41 -07:00
Ross Thompson
7a824eaae1
Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
2022-03-24 23:47:28 -05:00
Ross Thompson
d347de8c49
dtim writes are supressed on non cacheable operation.
2022-03-12 00:46:11 -06:00
Ross Thompson
e802deb4d6
Can now support the following memory and bus configurations.
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1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
2022-03-11 15:18:56 -06:00
Ross Thompson
3dbf6790e1
Towards allowing dtim + bus.
2022-03-11 14:58:21 -06:00
Ross Thompson
11e5aad38a
Moved subcachelineread inside the cache. There is some ugliness to still resolve.
2022-03-11 12:44:04 -06:00
Ross Thompson
a12016e69b
Moved subcacheline read inside the cache.
2022-03-11 11:03:36 -06:00
Ross Thompson
326ecda060
removed unused parameter.
2022-03-11 10:43:54 -06:00
Ross Thompson
bdfca503fa
Name cleanup.
2022-03-10 18:44:50 -06:00
Ross Thompson
d77adbd673
Signal name cleanup.
2022-03-10 18:26:58 -06:00
Ross Thompson
50789f9ddd
Byte write enables are passing all configs now.
2022-03-10 17:26:32 -06:00
Ross Thompson
d5f524a15e
Added byte write enables to cache SRAMs.
2022-03-10 15:48:31 -06:00
Ross Thompson
acd60218b8
Removed unused signal.
2022-03-08 16:58:26 -06:00
Ross Thompson
cc21414051
Added parameter to spillsupport.
2022-03-08 16:38:48 -06:00
Ross Thompson
60e6c1ffa7
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
Ross Thompson
c23f6c7d90
Fixed bug with spill support and Instruction DA Page Faults.
2022-02-23 10:16:12 -06:00
Ross Thompson
62e1a97287
Added generates to pcnextf muxes for privileged and caches.
2022-02-22 22:45:00 -06:00
Ross Thompson
6a52f95cc8
Minor busdp cleanup.
2022-02-22 17:28:26 -06:00
Ross Thompson
ca59778c5a
Annotated IFU for mux changes.
2022-02-21 17:20:34 -06:00
Ross Thompson
62f5f1e622
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
c9e33208e3
Moved a few muxes around after sww changes.
2022-02-16 15:43:03 -06:00
Ross Thompson
71ed49bf2b
cleanup of signal names.
2022-02-16 15:29:08 -06:00
David Harris
caa4d83e57
t push
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-14 01:22:22 +00:00
Ross Thompson
1e7e59bdbd
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
David Harris
f5678e25db
Synthesis cleanup
2022-02-12 06:25:12 +00:00
Ross Thompson
2f2a4f4500
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
Ross Thompson
382d5fab0f
Cleanup.
2022-02-10 11:27:15 -06:00
Ross Thompson
3a0af5d9e9
Cleanup + critical path optimizations.
2022-02-10 11:11:16 -06:00
Ross Thompson
911ee36b22
Removed all possilbe paths to PreSelAdr from TrapM.
2022-02-09 19:20:10 -06:00
Ross Thompson
e0a605e95d
Cleanup IFU.
2022-02-08 14:54:53 -06:00
Ross Thompson
cecbb3362d
rv32e works for now. Still need to optimize.
2022-02-08 14:21:55 -06:00
Ross Thompson
39149c618f
Moved some muxes back into the bp.
2022-02-08 14:17:44 -06:00
Ross Thompson
d5d9bb9d4d
Temporary commit which gets the no branch predictor implementation working.
2022-02-08 14:13:55 -06:00
Ross Thompson
3cd067ac6a
Finished merge.
2022-02-08 11:36:24 -06:00
David Harris
0feb624bab
Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
2022-02-06 01:22:40 +00:00
Ross Thompson
1766c0f5ba
Removed unused ports from caches and buses.
2022-02-04 22:52:51 -06:00
Ross Thompson
dce4f8a0e5
Cleanup.
2022-02-04 22:40:51 -06:00
Ross Thompson
53551ab533
Moved the hwdata mux back into the busdp.
2022-02-04 22:39:13 -06:00
Ross Thompson
34cf77797a
Merged together the two sub cache line read muxes.
...
One mux was used for loads and the other for eviction.
2022-02-04 22:30:04 -06:00
David Harris
23868a33bc
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
2022-02-05 04:16:18 +00:00
Ross Thompson
c846368537
Moved the sub cache line read logic to lsu/ifu.
2022-02-04 20:42:53 -06:00
David Harris
bdf1a8ba73
changed DMEM and IMEM configurations to support BUS/TIM/CACHE
2022-02-03 00:41:09 +00:00
Ross Thompson
910d16b642
More cleanup of IFU.
2022-02-01 14:32:27 -06:00
Ross Thompson
dce9ee12b4
IFU and LSU now share the same busdp module.
2022-01-31 16:25:41 -06:00
Ross Thompson
a04aa283cb
partial ifu cleanup.
2022-01-31 16:08:53 -06:00
Ross Thompson
b05abc1795
cleanup.
2022-01-31 13:29:04 -06:00
Ross Thompson
d52c5b0393
LSU and IFU cleanup.
2022-01-28 15:26:06 -06:00
Ross Thompson
de0bef4f5b
Updated wave.do to match the ifu/lsu changes.
2022-01-28 14:37:15 -06:00
Ross Thompson
147d71fd46
Clean up of mmu instances in IFU and LSU.
2022-01-28 14:02:05 -06:00
Ross Thompson
4a8d0cb981
Moved spills to own module.
2022-01-28 13:40:35 -06:00
Ross Thompson
7fedc6b878
Cleaned up the InstrMisalignedFault.
2022-01-28 13:19:24 -06:00
Ross Thompson
1bb8d36308
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
David Harris
87aa0724a2
IFU cleanup
2022-01-27 17:18:55 +00:00
David Harris
218ff3e25d
IFU cleanup
2022-01-27 16:41:57 +00:00
David Harris
1c22077841
Optimized out second adder from IFU for PC+2
2022-01-27 16:06:24 +00:00
Ross Thompson
75c33bc6c9
BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush.
2022-01-27 07:59:59 -06:00
Ross Thompson
c3a78553be
Removed mux in PCNextF logic. Minor IFU improvements.
2022-01-26 22:33:26 -06:00
Ross Thompson
23c4ba2777
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
Ross Thompson
2c982dca03
IFU simplifications.
2022-01-26 13:54:59 -06:00
Ross Thompson
728e46a794
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-25 19:21:04 -06:00
David Harris
22c84dcd80
simpleram simplification
2022-01-25 19:46:13 +00:00
David Harris
f07123ff0f
simpleram simplification
2022-01-25 18:26:31 +00:00
David Harris
5eb71a3bbe
simpleram address simplification
2022-01-25 18:00:50 +00:00
David Harris
d9888c91a6
simpleram clk and reset simplification
2022-01-25 17:34:15 +00:00
