bbracker
8554f2f3cd
plic implementation optimizations
2021-05-19 18:10:48 +00:00
bbracker
fd4fae0406
commented out MSTATUS test
2021-05-19 12:38:01 -04:00
James E. Stine
058b265d18
Update rv64icfd batch script
2021-05-18 16:01:53 -05:00
James E. Stine
f407bee5ae
Mod to config to properly add FP stuff - for icfd test. Should not change regression test through Imperas as just mod to testbench (add tests64d/tests64f but remove from MISA)
2021-05-18 13:48:44 -05:00
bbracker
18ab9015f9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-18 14:33:40 -04:00
bbracker
f43ea946aa
changed lint script to use absolute path for verilator because cron jobs stink at using paths
2021-05-18 14:33:22 -04:00
David Harris
7dcc53dcf5
fixed rv64mmu makefile
2021-05-18 14:25:55 -04:00
David Harris
5f214d60b6
Removed rv64wally
2021-05-18 14:08:46 -04:00
David Harris
433ea61d9e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
...
Conflicts:
wally-pipelined/regression/vish_stacktrace.vstf
2021-05-18 14:01:19 -04:00
bbracker
9b3332f3c3
commented changes to imperas makefiles
2021-05-18 13:34:48 -04:00
Katherine Parry
409438bc95
floating point infinite loop removed from imperas tests
2021-05-18 10:42:51 -04:00
bbracker
c08f5e6732
script for running make and logging output
2021-05-17 22:12:18 -04:00
bbracker
31c29b0cf1
changed makefiles so that make stops at bad source code that does not compile
2021-05-17 21:20:30 -04:00
bbracker
86d55cd07a
fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions
2021-05-17 19:25:54 -04:00
bbracker
69ef758e78
regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench
2021-05-17 18:44:47 -04:00
David Harris
1aa1908994
Deleted vish_stacktrace
2021-05-17 18:39:01 -04:00
David Harris
42483e5e03
Started MSTATUS tests
2021-05-17 18:37:56 -04:00
James E. Stine
49cc330bd9
Forgot initialization config for div - apologies
2021-05-17 17:12:27 -05:00
Elizabeth Hedenberg
853c9243c1
commit ehedenberg coremark
2021-05-17 18:02:35 -04:00
Elizabeth Hedenberg
9d17950c1d
coremark commit ehedenberg final
2021-05-17 18:02:34 -04:00
James E. Stine
96eca3287f
Add 32/64-bit shifter for update to shifter block
2021-05-17 17:02:13 -05:00
James E. Stine
8822bdd6ad
Cleanup of regression
2021-05-17 16:58:15 -05:00
James E. Stine
41da78e0b6
Mod Imperas Testbench for updated Div/Rem
2021-05-17 16:56:30 -05:00
James E. Stine
97cbdae674
Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
2021-05-17 16:48:51 -05:00
Thomas Fleming
fda439b51e
Fix comment
2021-05-14 08:06:07 -04:00
Thomas Fleming
a191978a97
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-14 07:40:08 -04:00
Thomas Fleming
1fc607b399
Remove busy-mmu and fix missing signal
2021-05-14 07:14:20 -04:00
Thomas Fleming
980c00fa64
Clean up MMU code
2021-05-14 07:12:32 -04:00
Elizabeth Hedenberg
0fe798d5e1
pushing coremark to main branch
2021-05-11 21:33:39 -04:00
Elizabeth Hedenberg
038902a4ef
coremark integration into main
2021-05-11 21:33:38 -04:00
Jarred Allen
dc41623754
Minor fixes in regression
2021-05-09 13:57:09 -04:00
Jarred Allen
788680fa4d
Fix bug in regression script
2021-05-06 12:56:57 -04:00
Domenico Ottolia
f78f865e88
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 20:22:31 -04:00
Domenico Ottolia
1c884338b0
Forgot to add csr permission tests to testbench
2021-05-04 20:20:22 -04:00
Jarred Allen
15da77fe15
Clean up regression script and document it
2021-05-04 18:58:59 -04:00
ushakya22
6274c8cb80
Added mip tests to testbench
2021-05-04 15:36:06 -04:00
Thomas Fleming
1e0a5ef807
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 15:22:21 -04:00
bbracker
535046e494
small synthesis fixes
2021-05-04 15:21:01 -04:00
Thomas Fleming
37bba95500
Fix compiler warning in PMP checker
2021-05-04 15:18:08 -04:00
Domenico Ottolia
14becde792
Re-add medeleg tests to testbench
2021-05-04 14:42:20 -04:00
Ross Thompson
619dcb165d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-04 13:04:20 -05:00
Ross Thompson
2aa4db470b
Fixed synthesis bug with icache valid bit.
2021-05-04 13:03:08 -05:00
ushakya22
6a71aafadc
Updated CSR tests
2021-05-04 13:48:47 -04:00
Ross Thompson
87d3869a6e
Fixed icache pcmux control for handling miss spill miss.
2021-05-04 11:05:01 -05:00
Thomas Fleming
192878b124
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-05-04 03:14:38 -04:00
Thomas Fleming
dac07e34cf
Fix bug in PMP checker
...
Now we only enforce PMP regions if at least one is non-null
2021-05-04 03:14:07 -04:00
ushakya22
da352c81e7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-05-04 02:22:17 -04:00
ushakya22
66344f0604
Added MIE tests to testbench
2021-05-04 02:22:01 -04:00
Thomas Fleming
d7fa0903bc
Disable PMP checker to fix test loops
...
There is a bug in the PMP checker where S or U mode attempts to make a
memory access while no PMP registers are set. We currently treat this as
a failure, when this should instead be allowed.
2021-05-04 01:56:05 -04:00
Domenico Ottolia
2c39c0a6a5
Minor tweaks to mcause & scause tests
2021-05-04 01:33:49 -04:00
