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Configurable RISC-V Processor
841 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.7%
Python 19.3%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
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Elizabeth Hedenberg 9d17950c1d coremark commit ehedenberg final
2021-05-17 18:02:34 -04:00
riscv-coremark coremark commit ehedenberg final 2021-05-17 18:02:34 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP Created special test for driving the instruction spill error. 2021-04-08 15:05:08 -05:00
wally-pipelined Add 32/64-bit shifter for update to shifter block 2021-05-17 17:02:13 -05:00
.gitignore Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor