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296 Commits 4 Branches 2 Tags 52 MiB
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Author SHA1 Message Date
David Harris
52d4a04eb0 Created atomic test vector and directories 2021-03-08 09:38:55 -05:00
Ross Thompson
a3759f585d Updated the paths to the branch predictor memory preloads for busy bear. 2021-03-05 15:36:00 -06:00
Ross Thompson
d6bc34121f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-05 15:27:22 -06:00
Ross Thompson
9a93193d6a Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Noah Boorstin
d3bf36b15f busybear: add branch preditor loading to do file 
(sorry to add more loading to the do instead of less)
 2021-03-05 21:01:41 +00:00
Noah Boorstin
f0a103687e Merge branch 'main' into busybear 2021-03-05 20:27:19 +00:00
Noah Boorstin
6981907521 fix wally-pipelined-batch.do to match wally-pipelined.do 2021-03-05 20:27:01 +00:00
bbracker
612f7a9ee4 added a delay to sel signals 2021-03-05 15:07:34 -05:00
bbracker
a1223ee13b more merging fixes 2021-03-05 14:36:07 -05:00
bbracker
2cd0f19129 remove deprecated mem signals 2021-03-05 14:27:38 -05:00
bbracker
420c9a11c2 refactored sim file 2021-03-05 14:25:16 -05:00
bbracker
62dd9e3075 first merge of ahb fix 2021-03-05 14:24:22 -05:00
Noah Boorstin
464c1de03d busybear: slight testbench update 2021-03-05 19:00:40 +00:00
Noah Boorstin
0af002eb2f busybear: make CSRs only weird for us 2021-03-05 00:46:32 +00:00
Noah Boorstin
7208b9bcf2 busybear: better implenetation of sim-busybear-batch 2021-03-05 00:39:03 +00:00
Ross Thompson
a982ad7a9a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 17:31:27 -06:00
Ross Thompson
7902c3fdb6 updated the function radix to look at wally signals. 2021-03-04 17:31:12 -06:00
Noah Boorstin
cfcd7d1518 busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Katherine Parry
5374dca1b9 fixed various bugs 2021-03-04 22:20:39 +00:00
Katherine Parry
4591b25c86 fixed various bugs 2021-03-04 22:20:28 +00:00
Katherine Parry
6fa2bc8efe fixed various bugs 2021-03-04 22:20:23 +00:00
Katherine Parry
10b179399c fixed various bugs 2021-03-04 22:20:02 +00:00
Katherine Parry
8e3b74c772 fixed various bugs 2021-03-04 22:19:21 +00:00
Katherine Parry
4e6b35c8b2 fixed various bugs 2021-03-04 22:18:47 +00:00
Katherine Parry
3c86d0912a fixed various bugs 2021-03-04 22:18:19 +00:00
Ross Thompson
5b7f0772ca Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 16:06:22 -06:00
Brett Mathis
b5a08e496f Pipelined functional units for FPU 2021-03-04 14:30:11 -06:00
Noah Boorstin
5c456e2d7f busybear: comment out instraccessfaultf for imem for now 2021-03-04 20:26:41 +00:00
Noah Boorstin
fde94f9057 Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00
Ross Thompson
619bbd9d83 Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Ross Thompson
a8cd4f2b2e Fixed forwarding around the 2 bit predictor. 2021-03-04 13:01:41 -06:00
bbracker
7852d866ef JALR testing 2021-03-04 10:37:30 -05:00
bbracker
5de23fcbe0 changed test maker to output trace files for debug 2021-03-04 10:36:04 -05:00
Ross Thompson
d0223da2f7 Converted to using the BTB to predict the instruction class. 2021-03-04 09:23:35 -06:00
Thomas Fleming
8c410b6fbe Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1a2db17ee5 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Thomas Fleming
ab6ae6d3f1 Merge branch 'tlb_toy' into main 2021-03-04 02:41:11 -05:00
Thomas Fleming
7a9f866120 Move tlb into mmu directory 2021-03-04 02:39:08 -05:00
Teo Ene
b15ef47d24 Fix to 32-bit option of commit 2d40898158 2021-03-04 01:33:34 -06:00
Thomas Fleming
d821a1dbfa Merge branch 'main' into tlb_toy 2021-03-04 01:18:04 -05:00
Thomas Fleming
c03b540956 Generalize tlb module 
- number of tlb entries is now parameterized
- tlb now supports rv64i
 2021-03-04 01:13:31 -05:00
Thomas Fleming
5fd521d333 Create virtual memory ad-hoc test 
Test program is currently failing on ovpsim. There is no indication that ovpsim
is properly implementing virtual memory translation when satp is set accordingly.
Need to confirm whether this is a problem with ovpsim, how ovpsim is being
called, or the test itself.
 2021-03-03 17:06:37 -05:00
Teo Ene
d3a1afe50e Fix to last push 2021-03-03 15:20:38 -06:00
Teo Ene
b50faef94d Updated coremark .do file for easier debugging 2021-03-03 15:10:39 -06:00
Teo Ene
e30645a4f1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-02 17:23:44 -06:00
Teo Ene
d02e22feac Updated coremark .do file for easier debugging 2021-03-02 17:23:39 -06:00
Noah Boorstin
beb2beabfd busybear: add sim-busybear and sim-busybear-batch based on sim-wally 2021-03-01 21:01:15 +00:00
Noah Boorstin
923489fe16 busybear: probably discovered bug in ahb code 2021-03-01 20:56:04 +00:00
Noah Boorstin
b6dc0a8707 busybear: only check pc when it actually changes 2021-03-01 19:08:35 +00:00
Noah Boorstin
b3247eadd2 busybear: more adapting to new memory system 2021-03-01 18:50:42 +00:00