Ross Thompson
517c0f6c35
Changed signal names.
2022-08-17 16:12:04 -05:00
Ross Thompson
f6e5746e59
Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
2022-08-17 16:09:20 -05:00
Ross Thompson
299aefb76a
Removed old code from interlockfsm.
2022-08-17 12:52:56 -05:00
Ross Thompson
57fcf0ef79
Fixed fstore2 in cache?
2022-08-01 22:04:44 -05:00
Ross Thompson
797d9e3610
Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.
2022-08-01 21:12:25 -05:00
Ross Thompson
3cd8404917
Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
2022-08-01 21:08:14 -05:00
Ross Thompson
3612db2d70
pulled swbbytemask out of subword write.
2022-08-01 20:48:45 -05:00
Ross Thompson
40e7cda84a
Don't use this commit yet. Untested.
2022-07-24 15:40:52 -05:00
Ross Thompson
719b00e338
Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.
2022-07-24 01:20:29 -05:00
Ross Thompson
05484c4c05
signal name cleanup.
2022-07-22 23:36:27 -05:00
Katherine Parry
12a54161c0
found the bug in the store modification
2022-07-12 22:42:19 +00:00
Katherine Parry
62205ebb3b
renamed FLoad2 to FStore2
2022-07-09 00:26:45 +00:00
Katherine Parry
97e7e619d9
moved fpu ieu write data mux to lsu
2022-07-08 23:56:57 +00:00
David Harris
72e216d053
APB CLINT passing regression
2022-07-05 15:51:35 +00:00
Katherine Parry
8f98f3bfab
added rv32 double precision stores - untested
2022-06-28 21:33:31 +00:00
Katherine Parry
03d823f5d7
added fld in rv32 - needs testing
2022-06-20 22:53:13 +00:00
slmnemo
a21d731834
Added more comments
2022-06-13 12:26:08 -07:00
slmnemo
9f4ca06f7f
Added comment about name of LSUBusInit/Lock signal
2022-06-13 10:56:02 -07:00
slmnemo
a79737e95b
Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
2022-06-10 20:43:56 -07:00
slmnemo
d6a1ee1141
Added comments to signals added so the bus is easier to analyze
2022-06-10 20:30:04 -07:00
slmnemo
31852fdb19
Fixed failed regression state by only enabling counting when doing cached operations
2022-06-10 20:00:09 -07:00
slmnemo
0e10435fb6
Fixed error where CntReset would be high one cycle too long, adding a cycle of delay. Broke wally64priv by failing trap-sret-01.
2022-06-10 19:10:01 -07:00
slmnemo
5ac17eca1d
Passed Regression: Seems to work perfectly fine
2022-06-09 18:21:13 -07:00
slmnemo
a4c7d1d936
?
2022-06-09 17:50:47 -07:00
slmnemo
c4bc608268
Changes made on 9th Jun
2022-06-09 17:33:51 -07:00
slmnemo
8ae57f075f
Fixed error when doing uncached accesses where HTRANS was always 2
2022-06-08 18:58:07 -07:00
slmnemo
1605544bfc
Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.
2022-06-08 17:34:02 -07:00
slmnemo
dd33f2a009
Working version: Fixed error where Word count would always increment even without AHB to bus ACK
2022-06-08 15:29:32 -07:00
slmnemo
be658d3933
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
2022-06-08 15:03:15 -07:00
slmnemo
a5aa75e5de
Merge branch 'main' into cacheburstmode
2022-06-08 02:21:33 +00:00
slmnemo
1d22fc707a
Added lock signal to ensure AHB speaks with the right bus
2022-06-08 02:19:21 +00:00
slmnemo
85801e75db
Fixed off-by-one error in busdp capture
2022-06-07 19:36:39 +00:00
slmnemo
90c5e5d319
Reworked bus to handle burst interfacing
2022-06-07 11:22:53 +00:00
David Harris
129fab3794
Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
2022-06-02 14:18:55 +00:00
slmnemo
108f32e9df
Fixed double assignment on LSUBurstType
2022-06-01 01:04:49 +00:00
slmnemo
bddc32ed21
changed ahb FSM and caught potential bug in ack/wordcountthreshold when on last word
2022-05-26 18:41:27 -07:00
slmnemo
efce3e4953
added LSUBurstDone signal to signal when a burst has finished
2022-05-26 16:29:13 -07:00
slmnemo
ae460eccd4
Added signal to monitor HBURST and comments for each burst in busdp
2022-05-26 13:35:49 -07:00
slmnemo
80965f953c
added burst size signals to the IFU, EBU, LSU, and busdp
2022-05-25 18:02:50 -07:00
David Harris
5acb526375
More unused signal cleanup
2022-05-12 15:21:09 +00:00
David Harris
fb725a9e0a
Clean up unused signals
2022-05-12 14:49:58 +00:00
David Harris
b869190161
endian swapper
2022-05-08 06:51:50 +00:00
David Harris
8066ba45e8
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
David Harris
462158ea92
LSU name cleanup
2022-04-18 03:18:38 +00:00
David Harris
2882460c94
Renamed FinalAMOWriteDataM to AMOWriteDataM
2022-04-18 01:30:03 +00:00
David Harris
2819a1c305
Remvoed bytemask anding from FinalWriteDataM in subwordwrite
2022-04-17 22:33:25 +00:00
Ross Thompson
b9a19304db
Fixed possible bugs in LRSC.
2022-04-16 14:45:31 -05:00
Ross Thompson
ab9738d3be
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
02d6829f8e
Found the complex TrapM giving back the wrong instruction bug.
...
As I was reviewing the busfsm I found a typo.
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
It should be
assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event. Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into. The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation. IgnoreRequest is is high if there is a TrapM | ITLBMissF. Without the & ~IgnoreRequest the invalid address translation makes the request.
2022-04-11 13:07:52 -05:00
Ross Thompson
3ac736e2d5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-03-30 11:09:44 -05:00
