slmnemo 8ae57f075f Fixed error when doing uncached accesses where HTRANS was always 2		2022-06-08 18:58:07 -07:00
..
atomic.sv	Clean up unused signals	2022-05-12 14:49:58 +00:00
bigendianswap.sv	endian swapper	2022-05-08 06:51:50 +00:00
busdp.sv	Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors	2022-06-08 15:03:15 -07:00
busfsm.sv	Fixed error when doing uncached accesses where HTRANS was always 2	2022-06-08 18:58:07 -07:00
dtim.sv	Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.	2022-03-30 11:04:15 -05:00
interlockfsm.sv	atomic cleanup.	2022-03-10 18:56:37 -06:00
lrsc.sv	Clean up unused signals	2022-05-12 14:49:58 +00:00
lsu.sv	Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors	2022-06-08 15:03:15 -07:00
lsuvirtmen.sv	Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.	2022-03-24 23:47:28 -05:00
subwordread.sv	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
subwordwrite.sv	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
swbytemask.sv	LSU name cleanup	2022-04-18 03:18:38 +00:00