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1,260 Commits 4 Branches 2 Tags 52 MiB
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Author SHA1 Message Date
David Harris
516b710db6 Fixed busybear by restoring InstrValidW needed by testbench 2021-07-13 14:17:36 -04:00
David Harris
9af5cef65a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:26:51 -04:00
David Harris
283c2cda0e added or.sv 2021-07-13 13:26:40 -04:00
Katherine Parry
b9edbb15eb Fixed writting MStatus FS bits 2021-07-13 13:22:04 -04:00
Katherine Parry
acdd2e4504 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
David Harris
3427d2b7d6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:19:24 -04:00
David Harris
68d1f87101 Fixed InstrValid from W to M stage for CSR performance counters 2021-07-13 13:19:13 -04:00
bbracker
90eb84cc61 updated buildroot make procedure to incorporate configs more robustly 2021-07-13 12:40:14 -04:00
bbracker
471fe8ab31 whoops I accidentally made main.config into a symbolic link; now it is a source file 2021-07-13 11:00:01 -04:00
bbracker
be81912c52 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 10:04:13 -04:00
bbracker
497d8e3f16 working config for a buildroot that boots 2021-07-13 10:04:09 -04:00
David Harris
4be1e8617f Replaced .or with or_rows structural code in MMU read circuitry for synthesis. 2021-07-13 09:32:02 -04:00
Katherine Parry
a4bd128978 fcvt.sv cleanup 2021-07-11 21:30:01 -04:00
Katherine Parry
0cc07fda1b Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
bbracker
05f9fa65bf rootfs.cpio no longer overlaps 2021-07-11 05:11:12 -04:00
bbracker
e77a9169b6 greatly stripped down unused stuff in linux config 2021-07-10 11:53:35 -04:00
David Harris
488cfa16ff Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 19:18:35 -04:00
David Harris
e6fb590187 added missing tlbmixer.sv 2021-07-09 19:18:23 -04:00
bbracker
4556098f0a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 18:56:28 -04:00
bbracker
e4f62e32ba fix_mem.py bugfix 2021-07-09 18:56:17 -04:00
bbracker
b2cb86d55c organize/update buildroot scripts for new image 2021-07-09 17:03:47 -04:00
David Harris
ef2bcf6ea7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 07:53:30 -04:00
David Harris
b09fd0d0a8 Simplified tlbmixer mux to and-or 2021-07-08 23:34:24 -04:00
David Harris
4d53a935b3 Fixed missing stall in InstrRet counter 2021-07-08 20:08:04 -04:00
bbracker
5736fdecbb organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files 2021-07-08 19:18:11 -04:00
David Harris
230654ea76 Eliminate reserved bits from TLB RAM 2021-07-08 17:35:00 -04:00
David Harris
f806707cb0 Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram 2021-07-08 16:58:11 -04:00
David Harris
b1592a0542 TLB cleanup to match diagrams 2021-07-08 16:52:06 -04:00
David Harris
dc44ca4b0b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-07 06:32:29 -04:00
David Harris
6dc49dd073 Renamed tlb ReadLines to Matches 2021-07-07 06:32:26 -04:00
Abe
09a092abd5 Updated MISA defining as well as porting sizes for peripherals (34 to 56) 2021-07-07 02:37:09 -04:00
Abe
ed3c06b851 Commented out printf statements for quicker simulation time. Also added function minstretDiff, which calculates the number of machine instructions retired during the coremark benchmark's runtime, excluding setup time. 2021-07-07 02:28:11 -04:00
Abe
ab61590f77 Removed debugging loop to test timers for clarity 2021-07-06 23:37:43 -04:00
Abe
63e4db1158 Updated portme file to include counters MTIME and MINSTRET. Timer currently set to read milliseconds running at 100MHZ, but this can be changed by setting a different clock speed in the testbench sv file and manipulating TIMER_RES_DIVIDER on line 120 2021-07-06 23:35:47 -04:00
Abe
244e197348 Changed SvMode to SVMode on line 76 2021-07-06 23:28:58 -04:00
David Harris
1301f4df7f Added ASID matching for CAM 2021-07-06 18:56:25 -04:00
Kip Macsai-Goren
1652e09b38 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 18:54:41 -04:00
David Harris
2b26bbbbd7 more TLB name touchups 2021-07-06 18:39:30 -04:00
Kip Macsai-Goren
8dfa28125f fixed upper bits page fault signal 2021-07-06 18:32:47 -04:00
David Harris
73024fee2d connected signals in tlb by name instead of .* 2021-07-06 17:22:10 -04:00
David Harris
18f4fa600a changed tlbphysicalpagemask to structural 2021-07-06 17:16:58 -04:00
David Harris
404ba5988a changed tlbphysicalpagemask to structural 2021-07-06 17:08:04 -04:00
David Harris
eb948f81dc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 15:29:49 -04:00
David Harris
78850bfcd8 MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB 2021-07-06 15:29:42 -04:00
Kip Macsai-Goren
794becd886 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 15:05:51 -04:00
Ross Thompson
dc4c26d2a2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-06 13:45:20 -05:00
Ross Thompson
d85bf23af3 Merged several of the load/store/instruction access faults inside the mmu. 
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
 2021-07-06 13:43:53 -05:00
bbracker
0e708a72f3 more completely uncomment MMU tests to make sim wally work 2021-07-06 14:33:52 -04:00
Kip Macsai-Goren
61fc9bb266 edited tests so regression would pass with float enabled. this IS NOT a comprehensive test for fs yet 2021-07-06 14:28:26 -04:00
Abe
79e62b7c53 Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140) 2021-07-06 12:37:58 -04:00