David Harris
5142bfd624
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-23 06:15:49 -07:00
David Harris
3407b63c8a
Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience.
2021-10-23 06:15:26 -07:00
Katherine Parry
00cc1e0c5c
put the FMA priority encoders into their own module
2021-10-22 10:03:12 -07:00
David Harris
4aeadaacf0
moved coemark and testsBP to tests
2021-10-20 09:10:06 -07:00
David Harris
47f7a5db9c
Fixed multiplier and pointed arch tests to new path in addins
2021-10-18 15:43:59 -07:00
James E. Stine
6b30adb309
Clean up some signals - beautification onging
2021-10-14 17:12:00 -05:00
Kip Macsai-Goren
ffcf5f5825
Fixed typo in imperas64mmu tests causing PMP tests not to run.
2021-10-14 13:42:24 -07:00
James E. Stine
eb64a7f0c9
Update to fpdivsqrt to go on posedge as it should. Also an update to
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individual regression test for TestFloat (still needs some tweaking)
2021-10-13 17:14:42 -05:00
bbracker
886a650da4
change infrastructure to expect only 6.3 million from buildroot
2021-10-12 10:41:15 -07:00
David Harris
a077735ecc
Major reorganization of regression and simulation and testbenches
2021-10-10 15:07:51 -07:00
James E. Stine
11cf3d97c5
Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH
2021-10-10 15:44:01 -05:00
bbracker
5a987cf0ca
use correct string formatting function
2021-10-10 10:09:59 -07:00
bbracker
54e0e8eb5b
make testbench-linux halt on some discrepancies with QEMUw
2021-10-09 17:22:30 -07:00
Kip Macsai-Goren
381a8fcd27
updated pmp output to correspond to test changes, commented out execute tests until cache/fence interaction works fully.
2021-10-08 15:40:18 -07:00
David Harris
7e340d16fd
moved fp vectors into vectors subdirectory
2021-10-07 23:28:06 -04:00
David Harris
626780381a
Included TestFloat and SoftFloat
2021-10-07 23:03:45 -04:00
James E. Stine
0c408a9816
update scripts
2021-10-07 15:14:54 -05:00
James E. Stine
4dcfcfacfc
TV for conversion and compare
2021-10-06 14:38:32 -05:00
James E. Stine
658dcc8c1b
Update to testbench for FP stuff
2021-10-06 13:16:38 -05:00
James E. Stine
4ece7b5341
Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included
2021-10-06 08:56:01 -05:00
Skylar Litz
a924e79e26
added delayed MIP signal
2021-10-04 18:23:31 -04:00
David Harris
bf0061be66
Reduced cycle count for DIVW/DIVUW by two
2021-10-03 09:42:22 -04:00
David Harris
30ec68d567
Parameterized number of bits per cycle for integer division
2021-10-03 01:10:15 -04:00
David Harris
73d852b1ef
Divide performs 2 steps per cycle
2021-10-02 09:19:25 -04:00
David Harris
35e5a5cef3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 23:15:34 -04:00
bbracker
5022647041
Revert "first attempt at verilog side of checkpoint functionality"
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This reverts commit f6ef8e5656
2021-09-30 20:45:26 -04:00
David Harris
a39e14663d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 20:07:43 -04:00
David Harris
e1ad732178
SRT Division unsigned passing Imperas tests
2021-09-30 12:17:24 -04:00
bbracker
f6ef8e5656
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
bbracker
2ffdbdf6d2
condense testbench code; debug_level of 0 means don't check at all
2021-09-27 03:03:11 -04:00
bbracker
441759b81c
switch testbench-linux's interrupts from xcause to mip and improve warning messages
2021-09-22 12:33:11 -04:00
bbracker
b1be8f4858
fix regression
2021-09-15 17:30:59 -04:00
David Harris
e32ab128e9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-13 12:41:07 -04:00
David Harris
654f3d1940
Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
2021-09-13 12:40:40 -04:00
Ross Thompson
d4c87d17b2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-13 09:41:34 -05:00
David Harris
1847198da9
Cleaned up wally-arch test scripts
2021-09-13 00:02:32 -04:00
Ross Thompson
144003cb41
FPGA test bench and test program.
2021-09-12 20:41:54 -05:00
David Harris
cb624fe679
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
David Harris
a31828e925
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-08 16:00:12 -04:00
David Harris
30e2ec3987
Added testbench-arch for riscv-arch-test suite
2021-09-08 15:59:40 -04:00
Ross Thompson
6606eea27e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-08 12:47:03 -05:00
bbracker
5e9a39e755
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
bbracker
b3f00f2682
make testbench successfully deactivate TimerIntM so as to create a nice pulse
2021-09-07 15:36:47 -04:00
bbracker
28fed18421
No longer forcing CSRReadValM because that can feedback to corrupt some CSRs
2021-09-06 22:59:54 -04:00
bbracker
a13b561759
modified testbench to not allow Wally to generate its own interrupts (because of fundamental interrupt imprecision limitations)
2021-09-04 19:49:26 -04:00
Ross Thompson
b3849d8abb
Moved data path logic from icacheCntrl to icache.
2021-08-26 10:58:19 -05:00
Ross Thompson
c48556836b
Removed generate around the dcache memories.
2021-08-25 13:27:26 -05:00
Ross Thompson
b7972eafeb
Added function tracking to linux test bench.
2021-08-24 11:08:46 -05:00
Ross Thompson
97653e1aea
Wally previously was overcounting retired instructions when they were flushed.
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InstrValidM was used to control when the counter was updated. However this is
not suppress the counter when the instruction is flushed in the M stage.
2021-08-23 12:24:03 -05:00
Ross Thompson
b6e2710f5d
Confirmed David's changes to the interrupt code.
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When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine. This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege. Since the CPU
is currently in machine mode the interrupt must be taken if MIE.
Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
2021-08-22 21:36:31 -05:00
