Ross Thompson
|
1d7002e5c5
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-11-03 17:36:04 -05:00 |
|
Ross Thompson
|
ccce0df535
|
Potentially a valid zero stage boot loader based on cva6.
|
2022-11-03 17:35:57 -05:00 |
|
Ross Thompson
|
103514a8e0
|
More outline for uart timeout interrupt.
|
2022-10-28 13:53:56 -05:00 |
|
Ross Thompson
|
21eca47d2e
|
Untested change to uart test for outline of how to handle rx fifo timeout.
|
2022-10-28 13:31:16 -05:00 |
|
Kip Macsai-Goren
|
6e45698b86
|
Added test for UART FIFO timeout. Does not pass regression
|
2022-10-25 05:35:56 +00:00 |
|
Ross Thompson
|
a59df0c77d
|
Created one off test to replicate the floating point forwarding hazard bug.
|
2022-10-22 16:29:12 -05:00 |
|
Kip Macsai-Goren
|
c18c181fc0
|
fixed endianness mstatush problem, passes make, not regression
|
2022-10-04 17:37:39 +00:00 |
|
Kip Macsai-Goren
|
e603973dff
|
added xlen and endianness test edits. xlen passes but endinanness still won't make
|
2022-09-26 05:03:19 +00:00 |
|
Kip Macsai-Goren
|
9821a50eaa
|
added mstatus uxl, sxl bit tests (not tested in regression yet)
|
2022-09-18 00:11:29 +00:00 |
|
Kip Macsai-Goren
|
0cc7f5719c
|
ported endianness tests to 32 bits (not tested in regression yet)
|
2022-09-18 00:10:29 +00:00 |
|
Kip Macsai-Goren
|
c5cbe43732
|
Fixed typos in existing endianness test
|
2022-09-18 00:09:52 +00:00 |
|
Kip Macsai-Goren
|
e6987524ab
|
added full coverage of subword loads and stores to endianness test
|
2022-09-17 23:14:38 +00:00 |
|
Kip Macsai-Goren
|
cc7d1c8ef9
|
Created initial endianness tests
|
2022-09-16 01:06:26 +00:00 |
|
David Harris
|
898dbc8e74
|
Completed PLIC-S tests. Regression working. This completes peripheral tests.
|
2022-08-03 09:33:56 -07:00 |
|
David Harris
|
4fb467ee8a
|
Debugging plic-s test
|
2022-08-03 13:21:09 +00:00 |
|
David Harris
|
7e5b78f240
|
plic-s debug
|
2022-08-03 12:33:09 +00:00 |
|
David Harris
|
cab0349701
|
Started plic-s tests
|
2022-08-03 03:48:08 +00:00 |
|
David Harris
|
93d7d7179e
|
Added parity and stop bit tests to UART
|
2022-07-28 04:35:51 +00:00 |
|
David Harris
|
429bdae1c4
|
Fixed UART reference output
|
2022-07-27 22:16:38 +00:00 |
|
David Harris
|
b08c87cb47
|
Finished UART test
|
2022-07-27 04:06:59 +00:00 |
|
David Harris
|
75a265159b
|
Increased timeout threshold to avoid timeout building riscof tests on slow machine
|
2022-07-27 04:05:21 +00:00 |
|
slmnemo
|
7348af7fd5
|
Updated reference file for UART test
|
2022-07-26 09:39:31 -07:00 |
|
slmnemo
|
a9d5805990
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-26 09:15:20 -07:00 |
|
slmnemo
|
5218865a7f
|
Committing changes made to UART test
|
2022-07-26 09:14:40 -07:00 |
|
David Harris
|
2d7f4b133c
|
More work toward riscof tests
|
2022-07-26 06:19:13 -07:00 |
|
David Harris
|
c6a58eb5b6
|
Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd
|
2022-07-25 16:23:10 -07:00 |
|
David Harris
|
416f5edfe0
|
More riscof makefile tuning
|
2022-07-25 21:15:56 +00:00 |
|
David Harris
|
7f7b3359b0
|
Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings
|
2022-07-25 20:50:38 +00:00 |
|
slmnemo
|
bfced6bfe8
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-07-22 17:13:38 -07:00 |
|
slmnemo
|
ca4511b6dc
|
Fixed UART FIFO bugs and added FIFO tests
|
2022-07-22 17:13:19 -07:00 |
|
Daniel Torres
|
d0aaae26fe
|
fixed wally rv32e tests, updated regression makefile to new testflow
|
2022-07-22 17:09:46 -07:00 |
|
Daniel Torres
|
4da96c5791
|
fixed 32priv tests, now passing
|
2022-07-22 15:35:20 -07:00 |
|
Daniel Torres
|
24828db612
|
changes to test.vh for compatability
|
2022-07-22 15:00:48 -07:00 |
|
Daniel Torres
|
4198145ce2
|
added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail
|
2022-07-22 14:58:55 -07:00 |
|
slmnemo
|
141f2a40e4
|
UART updates and PMA fix
|
2022-07-22 14:49:03 -07:00 |
|
slmnemo
|
9cca567136
|
Added test comments to reference output
|
2022-07-22 12:35:59 -07:00 |
|
Daniel Torres
|
0e75142ef4
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-22 11:16:09 -07:00 |
|
Daniel Torres
|
95fdd408ee
|
commiting current changes to riscof wally tests
|
2022-07-22 11:14:04 -07:00 |
|
slmnemo
|
d38369e8bf
|
Added new PLIC and UART tests
|
2022-07-22 07:12:55 -07:00 |
|
slmnemo
|
df568fd202
|
Added PLIC and UART tests and new functions to the test library
|
2022-07-22 07:10:39 -07:00 |
|
Daniel Torres
|
8dcb794bbb
|
added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64
|
2022-07-21 20:58:58 -07:00 |
|
Daniel Torres
|
635a02cf6a
|
made makefile more specific, just incase future additions
|
2022-07-21 12:50:02 -07:00 |
|
Daniel Torres
|
a8faddf81f
|
removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes
|
2022-07-21 12:47:51 -07:00 |
|
slmnemo
|
37bf837d48
|
fixed GPIO test by adding a new function to clear PLIC interrupts
|
2022-07-19 08:59:16 -07:00 |
|
Daniel Torres
|
4883bbb952
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-07-18 12:13:48 -07:00 |
|
Daniel Torres
|
6a77ada908
|
added the sail change to spike to let it all run normally
|
2022-07-18 12:13:15 -07:00 |
|
Katherine Parry
|
ac2ad1d60a
|
fixed uncommented line in makefile
|
2022-07-14 00:01:07 +00:00 |
|
Katherine Parry
|
12a54161c0
|
found the bug in the store modification
|
2022-07-12 22:42:19 +00:00 |
|
Katherine Parry
|
18d7fee541
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
|
2022-07-12 22:37:20 +00:00 |
|
Katherine Parry
|
97e7e619d9
|
moved fpu ieu write data mux to lsu
|
2022-07-08 23:56:57 +00:00 |
|
slmnemo
|
e190aeb14b
|
Fixed error in gpio test
|
2022-07-08 02:27:16 -07:00 |
|
Katherine Parry
|
7771f7b3eb
|
added load and store test
|
2022-07-07 21:48:51 +00:00 |
|
slmnemo
|
4fa4aaa7af
|
Resolved conflicts between different gpio files
|
2022-07-05 18:38:52 -07:00 |
|
slmnemo
|
6b2125ab0e
|
Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests.
|
2022-07-05 18:21:17 -07:00 |
|
David Harris
|
714a3fa962
|
Fixed typos in gpio test comments
|
2022-07-05 04:57:42 +00:00 |
|
David Harris
|
8612465756
|
fixed tininess detection in TestFloat examples, merged change in WALLY-TEST-LIB
|
2022-07-04 03:21:04 +00:00 |
|
slmnemo
|
0a774d9bf3
|
Fixed make error
|
2022-07-01 16:28:29 -07:00 |
|
Daniel Torres
|
d1eebac73f
|
reverted tests.vh to work on existing flow, added commented out paths to new riscof tests once that build has finished
|
2022-06-29 12:32:30 -07:00 |
|
Daniel Torres
|
2ae22ac6cb
|
added changes to testbench, tests and riscof for additional riscof compatability
|
2022-06-29 12:23:40 -07:00 |
|
slmnemo
|
f21c3114fd
|
Added termination line to CLINT test
|
2022-06-27 20:16:29 -07:00 |
|
slmnemo
|
228028c837
|
Add CLINT tests from book
|
2022-06-27 20:09:58 -07:00 |
|
slmnemo
|
7a5dba4b30
|
will this work in git
|
2022-06-27 18:59:44 -07:00 |
|
slmnemo
|
033ec135f8
|
Added reset read testcodes to GPIO
|
2022-06-27 18:56:35 -07:00 |
|
slmnemo
|
cb8ae72326
|
Fixed error in GPIO signature
|
2022-06-23 14:12:28 -07:00 |
|
David Harris
|
db459c3380
|
GPIO tests
|
2022-06-23 21:06:11 +00:00 |
|
slmnemo
|
d86a65daf0
|
Updating new GPIO tests
|
2022-06-23 13:22:00 -07:00 |
|
slmnemo
|
33c78e2404
|
Fixed wally-periph, regression is now working
|
2022-06-23 13:08:15 -07:00 |
|
slmnemo
|
80a57d0469
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-06-21 02:16:26 -07:00 |
|
slmnemo
|
b2cea45de0
|
Added rudimentary GPIO test according to testplans in chapter 15
|
2022-06-21 02:16:21 -07:00 |
|
Katherine Parry
|
03d823f5d7
|
added fld in rv32 - needs testing
|
2022-06-20 22:53:13 +00:00 |
|
Daniel Torres
|
1d4c543f71
|
arch tests now run on spike and sail and compare signatures during build
|
2022-06-17 20:53:15 -07:00 |
|
Daniel Torres
|
0ede7c412e
|
removed old code from makefile, simplified code in testbench
|
2022-06-17 15:13:38 -07:00 |
|
Daniel Torres
|
475220a5ff
|
arch bug fixes and testbench changes
|
2022-06-17 15:07:16 -07:00 |
|
Daniel Torres
|
83cce676a0
|
added files needed for arch to build
|
2022-06-16 18:05:06 -07:00 |
|
Katherine Parry
|
5f7072bd96
|
postprocessing unit created and passing all tests
|
2022-06-13 22:47:51 +00:00 |
|
DTowersM
|
b586e3af37
|
added some comments to help debuggers in the future
|
2022-06-10 01:44:52 +00:00 |
|
DTowersM
|
4e5d7ec3d6
|
changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability
|
2022-06-10 00:37:53 +00:00 |
|
Katherine Parry
|
b6b3f04af2
|
added create all vectores file
|
2022-06-02 21:56:47 +00:00 |
|
Katherine Parry
|
c5bde75e30
|
added createallvectors
|
2022-06-02 21:56:05 +00:00 |
|
Katherine Parry
|
c264585fe8
|
single and double conversions pass all tests
|
2022-05-25 23:02:02 +00:00 |
|
Kip Macsai-Goren
|
c210fb6b93
|
Added missing DEADBEEFs to this test as well
|
2022-05-12 22:31:26 +00:00 |
|
Kip Macsai-Goren
|
553e7bfeb9
|
Fixed priv test reference outputs to have the right number of "DEADBEEF"s (1024)
|
2022-05-12 22:30:14 +00:00 |
|
David Harris
|
73a84f28b9
|
Moved some privileged tests to be simulated.
|
2022-05-12 04:45:41 +00:00 |
|
David Harris
|
c100c9893b
|
wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts
|
2022-05-05 14:37:21 +00:00 |
|
Kip Macsai-Goren
|
8f748c4014
|
clarified some trap causing functions to use zzero register rather than li [reg] 0x0. Also updated signatures' tvals
|
2022-05-04 23:01:23 +00:00 |
|
Kip Macsai-Goren
|
88173b8bb3
|
added explicit clears to mstatus.mie
|
2022-05-04 23:00:17 +00:00 |
|
Kip Macsai-Goren
|
6a182efe0f
|
Updated test libraries to reflect variable name changes
|
2022-05-04 21:39:36 +00:00 |
|
Kip Macsai-Goren
|
6a372b1a1d
|
renamed test_loop_setup to run_test_loop
|
2022-05-04 21:39:09 +00:00 |
|
Kip Macsai-Goren
|
393edc9fd8
|
renamed debug to extended signature
|
2022-05-04 21:38:37 +00:00 |
|
Kip Macsai-Goren
|
0f70e48b6b
|
updated makefrag and tests.vh to reflect removed tests, new names
|
2022-05-04 21:20:25 +00:00 |
|
Kip Macsai-Goren
|
923cbc59a3
|
removed fp-diabled test and leftover mimpid test
|
2022-05-04 21:20:25 +00:00 |
|
Kip Macsai-Goren
|
3cab9f0234
|
removed instruction misaligned tests from trap tests, signatures
|
2022-05-04 21:20:25 +00:00 |
|
Kip Macsai-Goren
|
8c96672080
|
renamed all tests to have lower-case titles except for WALLY
|
2022-05-04 21:20:25 +00:00 |
|
Kip Macsai-Goren
|
208827502e
|
general test cleanup of comments and old files
|
2022-04-29 19:55:29 +00:00 |
|
Kip Macsai-Goren
|
7148429f4a
|
re-renamed status-mie-s to status-sie
|
2022-04-29 19:55:13 +00:00 |
|
Kip Macsai-Goren
|
e557e420b6
|
added missing SIE test
|
2022-04-29 19:54:29 +00:00 |
|
Kip Macsai-Goren
|
f50aa61994
|
renamed registers in test library to RISC-V ABI name rater than x2, etc..
|
2022-04-29 18:52:42 +00:00 |
|
Kip Macsai-Goren
|
5df381e26f
|
renamed PIE-stack tests to status-mie for clarity
|
2022-04-29 18:30:39 +00:00 |
|
Kip Macsai-Goren
|
c3ffcd0e95
|
removed old unused tests from wally arch tests
|
2022-04-28 18:14:08 +00:00 |
|
Kip Macsai-Goren
|
562296c677
|
added missing output for sret
|
2022-04-28 18:14:08 +00:00 |
|