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Author SHA1 Message Date
David Harris
1ffd30f2e1
Merge pull request #846 from ross144/main 
Removes *** from all system verilog
 2024-06-19 14:12:56 -07:00
Ross Thompson
685f4d3807 Removed the last of the ***. 2024-06-19 14:00:31 -07:00
Ross Thompson
2d8973df1d Updated wavefile to use new names. 2024-06-19 13:57:28 -07:00
Ross Thompson
64712d2243 Updated wave to match changes in testbench. 2024-06-19 13:51:50 -07:00
Ross Thompson
d368f2e77e Removed *** from testbench. 2024-06-19 13:51:37 -07:00
Ross Thompson
7f0ba87231 Updated comments in uart. 2024-06-19 13:51:30 -07:00
Ross Thompson
91c844ca45 Removed more *** from camline and csrc. 2024-06-19 12:31:50 -07:00
Ross Thompson
576f1b9e59 Moved the *** from trap to an issue. 2024-06-19 12:31:24 -07:00
Ross Thompson
9b6b6617af Cleaned up hptw. 2024-06-19 12:02:56 -07:00
Ross Thompson
24916d42e2 Refactored TLBMiss and TLBMissOrUpdateA(D) to simplify spill, ifu, lsu, and hptw. 2024-06-19 11:40:02 -07:00
Ross Thompson
71f267a17a Added InstrUpdateDAF to the HPTW. 2024-06-19 11:09:49 -07:00
Ross Thompson
77523c52c2 LSU no longer has ***. 2024-06-19 10:56:07 -07:00
Ross Thompson
5e5ca0809f Removed more *** from lsu and updated assertions for dtim. 2024-06-19 10:52:51 -07:00
Ross Thompson
4911642427 Removed *** and updated comments for bpred and align. 2024-06-19 10:31:44 -07:00
Ross Thompson
f0e5bbef0c Removed remaining *** from IFU. 2024-06-19 09:52:40 -07:00
Ross Thompson
cc58bfdcf3 Removed more *** from the ifu. 2024-06-19 09:49:17 -07:00
Ross Thompson
ab1ee3d69b Removed *** from IFU, lrcs. 2024-06-19 09:40:35 -07:00
Ross Thompson
c5dac4d775 Removed *** from fpga top. 2024-06-19 09:28:21 -07:00
Ross Thompson
ab1af0fabf Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2024-06-19 09:25:39 -07:00
David Harris
10e6d5846b Removed unnecessary Umfirst from early termination 2024-06-19 09:18:51 -07:00
David Harris
4b4980e42d Fixed undriven OutFmt 2024-06-19 09:17:32 -07:00
David Harris
54cb612577 Fixed lint error in fdivsqrtpreproc for rv32 IDIV_ON_FPU 2024-06-19 07:48:54 -07:00
David Harris
1f569ed6f8
Merge pull request #838 from jordancarlin/vcs_fix 
Update VCS RTL file exclusions with renamed ram
 2024-06-19 05:29:40 -07:00
Jordan Carlin
156bfc0387
Update f_fma tests to use smaller files from riscv-arch-test 2024-06-18 23:38:03 -07:00
Jordan Carlin
569ccfd829
Update riscv-arch-test submodule 2024-06-18 23:34:02 -07:00
Jordan Carlin
d58b454a8b
Finish switching Zfa to use riscv-arch-test 2024-06-18 23:31:37 -07:00
Jordan Carlin
00ccd80479
Update VCS RTL file exclusions with renamed ram 2024-06-18 22:47:00 -07:00
Jordan Carlin
955f5d831f
Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-06-18 22:39:05 -07:00
Ross Thompson
2581ea0b74 Found the actual bug. Once the ethernet transmit fifo was full the rvvi packetizer was not correctly marking the end of the frame. First Last was held for too many cycles. Second it was assert on cycles when Valid was not high. Simulation reproduced the FPGA corrupted frames and then with the fix showed working frames. 2024-06-18 16:48:49 -07:00
Rose Thompson
d2933edee4
Merge pull request #836 from davidharrishmc/dev 
Code Cleanup: Lint Improvements
 2024-06-18 08:56:17 -07:00
David Harris
301ded05f8 Unused signal cleanup 2024-06-18 08:15:48 -07:00
David Harris
cb563e8018 Clean up unused signals 2024-06-18 08:07:14 -07:00
Ross Thompson
00e0549c36 I know what is wrong now. The ethernet device IP is not correctly generating the mii nibble stream. Some nibbles are dropped in each 4-byte word. 
The default input interface to the interface is 8-bit and I used 32-bit.  I suspect there is a bug in the implementation for non-8-bit interfaces.
 2024-06-18 07:44:19 -07:00
David Harris
c1fd7a9589 Removed unused signals 2024-06-18 07:28:52 -07:00
Jordan Carlin
a493b9b131
Merge pull request #835 from davidharrishmc/dev 
Fixed Issue #752 of Verilator simulation by changing LRUMemory to be …
 2024-06-18 07:27:35 -07:00
David Harris
8bae52b09d Lint cleanup of unused signals 2024-06-18 06:49:17 -07:00
David Harris
45f505250c Lint cleanup 2024-06-18 06:23:43 -07:00
David Harris
3fa37b0233 Lint cleanup 2024-06-18 06:15:17 -07:00
David Harris
cac67aae4f Lint cleanup 2024-06-18 05:58:54 -07:00
David Harris
ecae1100f6 Lint cleanup 2024-06-18 05:49:49 -07:00
David Harris
7509e856df Removed asynchronous reset causing lint issue in peripherals 2024-06-18 05:49:12 -07:00
David Harris
2fc9edff45 Fixed Issue #752 of Verilator simulation by changing LRUMemory to be nonblocking now that Verilator handles this construct properly 2024-06-18 04:40:38 -07:00
Ross Thompson
93829ce509 Success! We have some instructions comparing across the FPGA and IDV! 
However I'm still losing ethernet frames.
 2024-06-17 13:41:40 -07:00
Ross Thompson
598770da51 Getting much closer to a working version. 2024-06-17 12:37:10 -07:00
Ross Thompson
cccb40e4b5 Got the tracer not overrunning ethernet buffers so frames are not being dropped. 2024-06-17 09:16:24 -07:00
Ross Thompson
82b54c0887 Got IDV properly initalized. 2024-06-17 09:15:59 -07:00
Rose Thompson
54c07265ba
Merge pull request #833 from davidharrishmc/dev 
Code cleanup in anticipation of code review
 2024-06-14 21:06:47 -07:00
David Harris
4a4bbdfc43 More code cleanup 2024-06-14 09:50:07 -07:00
David Harris
bfd3c9fe86 Fixed gettenvval when variable is undefined per verilator Issue 5179 2024-06-14 07:09:53 -07:00
David Harris
53477b2c85 Code cleanup 2024-06-14 07:08:17 -07:00