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Author	SHA1	Message	Date
David Harris	b9d177edc4	Merge pull request #819 from ross144/main ... wsim now supports directories	2024-06-01 18:57:17 +02:00
Rose Thompson	3da62558ec	Updated readme.	2024-06-01 11:12:30 -05:00
Rose Thompson	2382677f8f	Got the directory mode wsim working!	2024-06-01 10:56:37 -05:00
Rose Thompson	224b8469ab	Updated readme to reflect changes to wsim.	2024-06-01 09:58:10 -05:00
Rose Thompson	a78093274c	Simplified wsim so it automatically figures out if the second parameter is a testsuite or an elf file.	2024-06-01 09:56:50 -05:00
Rose Thompson	2a6c5a158f	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-06-01 09:50:18 -05:00
Rose Thompson	a830bd57f0	Have to reverse the byte order for ethernet frame length.	2024-05-31 17:46:43 -05:00
Rose Thompson	e05ebc30b8	Almost worked out the bugs in packetizer.	2024-05-31 16:48:41 -05:00
Rose Thompson	9ed78b5f08	Merge pull request #818 from JacobPease/main ... Added true bootloader to fpga/zsbl directory.	2024-05-31 15:34:08 -05:00
Jacob Pease	7a417d7a6c	Added true bootloader to fpga/zsbl directory.	2024-05-31 15:28:25 -05:00
Rose Thompson	0dccc6051d	draft of receiving code to unpack the ethernet frames into rvvi.	2024-05-31 13:55:25 -05:00
Rose Thompson	1df3e5239a	This is great. The FPGA is able to send ethernet frames consisting of the RVVI data to the host computer. ... wireshark is able to capture the frames and they match the expected data!	2024-05-30 17:57:28 -05:00
Rose Thompson	6a4c8667df	Added new signals to ILA to debug the RVVI tracer. ... The tracer appears to be stuck and the CPU is never getting out of (into reset).	2024-05-30 16:43:25 -05:00
Rose Thompson	ca90c6ba48	Added the ethernet files. These are part of another repo. ... We should remove before mainlining this.	2024-05-30 16:33:49 -05:00
Rose Thompson	38ddbf860e	Fixed bug with mmcm not generating the 4th clock.	2024-05-30 16:19:28 -05:00
Rose Thompson	24ba51370a	Merge pull request #817 from JacobPease/main ... The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.	2024-05-30 16:16:05 -05:00
Jacob Pease	3f7659c8ad	Removed old fpgaTop.v file.	2024-05-30 16:15:19 -05:00
Jacob Pease	6bf43ebe61	Merge branch 'main' of github.com:openhwgroup/cvw	2024-05-30 15:48:31 -05:00
Jacob Pease	7ecd1c7d5f	The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file.	2024-05-30 15:48:27 -05:00
Rose Thompson	9703055758	The FPGA is synthesizing with the rvvi and ethernet hardware.	2024-05-30 15:37:17 -05:00
Rose Thompson	f4626d5b06	Fixed bug so that wsim can start logging after a given number of instructions.	2024-05-29 14:50:09 -05:00
Rose Thompson	84946919a4	Changed name CacheWriteData to WriteData.	2024-05-28 18:00:39 -05:00
Rose Thompson	273b41df99	Changed name of cache parameter NUMLINES to NUMSETS to better match book.	2024-05-28 17:55:43 -05:00
David Harris	44f25186c6	Merge pull request #816 from ross144/main ... Merges support for functional coverage into wally.do and testbench.sv	2024-05-28 21:54:37 +02:00
Rose Thompson	a88d5f403b	Functional coverage works with wally.do	2024-05-28 14:02:54 -05:00
Rose Thompson	0c5b70c40a	It's a bit hacky. But I've got functional coverage working with our wally.do script and testbench.sv.	2024-05-28 13:54:48 -05:00
Rose Thompson	48fd365b9d	Still don't understand why wally.do can't load testbench.sv with functional coverage. But wally-imperas-cov.do can load testbench.sv with functional coverage.	2024-05-28 13:00:17 -05:00
Rose Thompson	4a1e856b18	Almost working functional coverage in wally.do ... riscvISACOV is now loading, but for some reason I still cannot get it to record anything. Instead it is just logging the instructions.	2024-05-27 18:15:12 -05:00
Rose Thompson	92ee56c1a1	Yay. Finally found the bug which prevented wally.do from having functional coverage using riscvISACOV. ... testbench.sv was missing the trace2cov instance.	2024-05-27 17:25:20 -05:00
Rose Thompson	4c0261fd2c	Closer. Needed to reorder includes and defines.	2024-05-27 15:37:16 -05:00
Jordan Carlin	6f79dca9c4	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-05-27 12:29:24 -07:00
Rose Thompson	ff611016c7	Closer?	2024-05-27 14:11:02 -05:00
Rose Thompson	26c6eec832	Getting closer to functional coverage integration.	2024-05-27 13:20:18 -05:00
Rose Thompson	2985cfb7eb	Preliminary work to merge functional coverage into wally.do.	2024-05-27 11:59:13 -05:00
Rose Thompson	c9b59c8b99	Merge pull request #815 from quswarabid/covergen ... Covergen	2024-05-27 10:42:29 -05:00
Quswar Abid	997b5901cc	sb types are all passing, loaditypes are not!	2024-05-27 04:27:50 -07:00
Quswar Abid	1bf9b13953	added some sb types	2024-05-27 03:58:38 -07:00
Quswar Abid	29d7cd5663	unwanted comments	2024-05-27 03:58:38 -07:00
Quswar Abid	8edc4057ed	compilable tests generating for loaditypes[lb, lh, lw, ld, lbu, lhu, lwu]	2024-05-27 03:58:38 -07:00
David Harris	14b9223390	Merge pull request #813 from jordancarlin/fround_fixes ... Fround fixes	2024-05-26 23:54:21 +02:00
Jordan Carlin	6f7a802b86	Merge branch 'main' of https://github.com/openhwgroup/cvw into fround_fixes	2024-05-26 14:40:26 -07:00
Jordan Carlin	b830d20f2d	Modify Fround Tmask to work for X=1	2024-05-25 12:56:02 -07:00
Rose Thompson	153e66c4bb	Merge pull request #810 from davidharrishmc/dev ... Zk simplification	2024-05-25 11:52:56 -05:00
Jordan Carlin	fb77440a64	Update fpctrl fmt to work for fround instructions	2024-05-24 15:33:45 -07:00
Jordan Carlin	ae29a9b861	Update control bits for froundnx	2024-05-24 15:19:20 -07:00
David Harris	cfe83f5b49	Added derived configs to test Zb* and Zk* individually	2024-05-24 15:18:36 -07:00
Jordan Carlin	dcafe4793e	Add froundnx and fround.d tests	2024-05-24 15:16:35 -07:00
Rose Thompson	dc09e1c0c5	Modified names so they don't conflict with FPGA's axi signals.	2024-05-24 16:38:47 -05:00
Rose Thompson	73261e7f89	More cleanup. Close to the simpliest it can be.	2024-05-24 16:34:33 -05:00
Rose Thompson	bd2ec879d2	Removed unused axi signals from packetizer.	2024-05-24 16:31:27 -05:00