8939 Commits

This Branch

This Branch

All Branches

Author	SHA1	Message	Date
Kevin Kim	eeea783da0	lint	2024-06-21 23:15:34 -07:00
Kevin Kim	4877633977	lint fixes tests vh	2024-06-21 22:16:09 -07:00
Kevin Kim	19f0cf7a35	putting back tests in tests vh	2024-06-21 21:51:44 -07:00
Kevin Kim	e6dc50308a	integer postprocessing hardware matches diagram	2024-06-21 21:50:55 -07:00
Kevin Kim	00bf3faa9c	changed intdivb width	2024-06-21 21:31:19 -07:00
Jordan Carlin	b76941d278	Use VCS built-in default macro instead of defining SIM_VCS	2024-06-21 15:17:59 -07:00
Kevin Kim	9a59c8e07f	reduced bit widths for integer on fpu	2024-06-20 23:46:45 -07:00
Rose Thompson	e1fc44a5bf	Merge pull request #849 from davidharrishmc/dev ... lint cleanup and divider optimization	2024-06-20 09:04:19 -07:00
David Harris	486e6ff0f6	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-06-20 08:43:48 -07:00
David Harris	d8d94eeafa	Merge pull request #808 from jordancarlin/main ... Update riscv-arch-test	2024-06-20 08:43:41 -07:00
Jordan Carlin	90f5a4ef48	Only run fmsub_b15 for f_fma test	2024-06-20 07:48:33 -07:00
David Harris	25780f53ce	Fixed Verilator testbench issue from FunctionName by rolling back to old if. PC=0 detection is disabled for now.	2024-06-20 00:57:58 -07:00
David Harris	27457f4ef4	Merge pull request #848 from ross144/main ... Covergen doesn't produce stores and riscv-dv only generates tests	2024-06-20 00:10:33 -07:00
David Harris	0ab3f28991	Lint cleanup	2024-06-20 00:10:03 -07:00
Ross Thompson	e88a2f7eaa	Merge branch 'main' of github.com:ross144/cvw into main	2024-06-19 15:14:28 -07:00
Ross Thompson	9e93f21990	Updated covergen to not include stores as they are incomplete. ... Modified makefile riscv-dv to not simulation only generate tests.	2024-06-19 15:13:49 -07:00
David Harris	5f1ee1ac85	Fixed undriven signal in certain config	2024-06-19 15:12:35 -07:00
David Harris	e4febf25ae	Merge pull request #847 from ross144/main ... Partial fix for verilator +args. At least compiles.	2024-06-19 14:27:39 -07:00
Rose Thompson	46ace521c6	Updated verilator makefile.	2024-06-19 16:25:31 -05:00
David Harris	9922b24cbe	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-06-19 14:13:08 -07:00
David Harris	1ffd30f2e1	Merge pull request #846 from ross144/main ... Removes *** from all system verilog	2024-06-19 14:12:56 -07:00
Ross Thompson	685f4d3807	Removed the last of the ***.	2024-06-19 14:00:31 -07:00
Ross Thompson	2d8973df1d	Updated wavefile to use new names.	2024-06-19 13:57:28 -07:00
Ross Thompson	64712d2243	Updated wave to match changes in testbench.	2024-06-19 13:51:50 -07:00
Ross Thompson	d368f2e77e	Removed *** from testbench.	2024-06-19 13:51:37 -07:00
Ross Thompson	7f0ba87231	Updated comments in uart.	2024-06-19 13:51:30 -07:00
Ross Thompson	91c844ca45	Removed more *** from camline and csrc.	2024-06-19 12:31:50 -07:00
Ross Thompson	576f1b9e59	Moved the *** from trap to an issue.	2024-06-19 12:31:24 -07:00
Ross Thompson	9b6b6617af	Cleaned up hptw.	2024-06-19 12:02:56 -07:00
Ross Thompson	24916d42e2	Refactored TLBMiss and TLBMissOrUpdateA(D) to simplify spill, ifu, lsu, and hptw.	2024-06-19 11:40:02 -07:00
Ross Thompson	71f267a17a	Added InstrUpdateDAF to the HPTW.	2024-06-19 11:09:49 -07:00
Ross Thompson	77523c52c2	LSU no longer has ***.	2024-06-19 10:56:07 -07:00
Ross Thompson	5e5ca0809f	Removed more *** from lsu and updated assertions for dtim.	2024-06-19 10:52:51 -07:00
Ross Thompson	4911642427	Removed *** and updated comments for bpred and align.	2024-06-19 10:31:44 -07:00
Ross Thompson	f0e5bbef0c	Removed remaining *** from IFU.	2024-06-19 09:52:40 -07:00
Ross Thompson	cc58bfdcf3	Removed more *** from the ifu.	2024-06-19 09:49:17 -07:00
Ross Thompson	ab1ee3d69b	Removed *** from IFU, lrcs.	2024-06-19 09:40:35 -07:00
Ross Thompson	c5dac4d775	Removed *** from fpga top.	2024-06-19 09:28:21 -07:00
Ross Thompson	ab1af0fabf	Merge branch 'main' of https://github.com/openhwgroup/cvw into main	2024-06-19 09:25:39 -07:00
David Harris	10e6d5846b	Removed unnecessary Umfirst from early termination	2024-06-19 09:18:51 -07:00
David Harris	4b4980e42d	Fixed undriven OutFmt	2024-06-19 09:17:32 -07:00
David Harris	54cb612577	Fixed lint error in fdivsqrtpreproc for rv32 IDIV_ON_FPU	2024-06-19 07:48:54 -07:00
David Harris	1f569ed6f8	Merge pull request #838 from jordancarlin/vcs_fix ... Update VCS RTL file exclusions with renamed ram	2024-06-19 05:29:40 -07:00
Jordan Carlin	156bfc0387	Update f_fma tests to use smaller files from riscv-arch-test	2024-06-18 23:38:03 -07:00
Jordan Carlin	569ccfd829	Update riscv-arch-test submodule	2024-06-18 23:34:02 -07:00
Jordan Carlin	d58b454a8b	Finish switching Zfa to use riscv-arch-test	2024-06-18 23:31:37 -07:00
Jordan Carlin	00ccd80479	Update VCS RTL file exclusions with renamed ram	2024-06-18 22:47:00 -07:00
Jordan Carlin	955f5d831f	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-06-18 22:39:05 -07:00
Rose Thompson	d2933edee4	Merge pull request #836 from davidharrishmc/dev ... Code Cleanup: Lint Improvements	2024-06-18 08:56:17 -07:00
David Harris	301ded05f8	Unused signal cleanup	2024-06-18 08:15:48 -07:00