Katherine Parry
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4a6abe0f50
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-02 12:56:53 -04:00 |
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Katherine Parry
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72406b8a88
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FPU update - missing files
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2021-07-02 12:53:05 -04:00 |
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David Harris
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1ce98cc100
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-02 12:52:20 -04:00 |
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Katherine Parry
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3f61e313d2
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FPU update
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2021-07-02 12:40:58 -04:00 |
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David Harris
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cd6cabac2f
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Optimized PMP checker logic and added support for configurable number of PMP registers
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2021-07-02 11:05:25 -04:00 |
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David Harris
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648c09e5ef
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Optimized PMP checker logic and added support for configurable number of PMP registers
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2021-07-02 11:04:13 -04:00 |
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Teo Ene
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c7c4916efd
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Correct physical implementation flow path
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2021-07-01 16:37:49 -05:00 |
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Teo Ene
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1d5d7a7840
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Flow updated for 90nm
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2021-07-01 13:32:42 -05:00 |
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Ross Thompson
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be6468c6d9
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Icache ITLB interlock fix.
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2021-06-30 19:24:59 -05:00 |
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Katherine Parry
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6216bd7172
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FPU control signals changed and FMA works
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2021-06-28 18:53:58 -04:00 |
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bbracker
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a7f810e2c4
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trying out Noah and Kaveh's proposed hack for which CSRs to update for QEMU MMU bug
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2021-06-26 08:30:58 -04:00 |
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bbracker
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61495f74ac
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-26 08:29:37 -04:00 |
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bbracker
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aa8da43743
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temporarily disable PMP checking for EBU accesses.
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2021-06-26 07:19:51 -04:00 |
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bbracker
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59b2a49854
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split intermediate GDB output file into smaller files for better debug experience
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2021-06-26 07:18:26 -04:00 |
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Abe
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b6426c5fbf
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Updated timing functions to read from MTIME register, TICKS_PER_SEC set to 10000 so timer reads millisecs
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2021-06-25 16:42:03 -04:00 |
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Abe
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ff8b421e6c
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Fixed Coremark Score output printing. Also made it so that the loop that sets the iteration count increments iterations by 1 instead by increasing it by a factor of 10 each time (which was overkill for the timing that's needed to exit the loop)
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2021-06-25 16:27:23 -04:00 |
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bbracker
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9927f771cc
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linux testbench now ignores HWRITE glitches caused by flush glitches
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2021-06-25 09:28:52 -04:00 |
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bbracker
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2694a7a43f
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made testbench-linux's PCDwrong be FlushD
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2021-06-25 08:15:19 -04:00 |
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bbracker
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4e09793a9a
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ah merge; I checked and this does pass all of regression except lints
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2021-06-25 07:37:06 -04:00 |
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bbracker
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aac9b46a1f
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changed SC M-to-E fowarding to W-to-E forwarding to improve critical path
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2021-06-25 07:18:38 -04:00 |
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Katherine Parry
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bc8d660bc5
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FPU forwarding reworked pt.1
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2021-06-24 18:39:18 -04:00 |
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bbracker
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ced5039776
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Revert "fixed forwarding"
This reverts commit 0f4a4a6ade.
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2021-06-24 17:39:37 -04:00 |
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bbracker
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0f4a4a6ade
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fixed forwarding
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2021-06-24 11:20:21 -04:00 |
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bbracker
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3ae4cd951a
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make linux testgen be nohup-friendly and make parser account for lr/sc memory accesses
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2021-06-24 08:35:00 -04:00 |
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bbracker
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3d6b422e34
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regression can overcome the fact that buildroots UART prints stuff
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2021-06-24 02:00:01 -04:00 |
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bbracker
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409a73604c
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whoops meant to remove notifications from busybear, not buildroot
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2021-06-24 01:54:46 -04:00 |
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bbracker
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55cf205222
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-24 01:42:41 -04:00 |
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bbracker
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b84419ff4e
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overhauled linux testbench and spoofed MTTIME interrupt
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2021-06-24 01:42:35 -04:00 |
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Katherine Parry
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44af47608c
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fpu clean-up
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2021-06-23 16:42:40 -04:00 |
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Ross Thompson
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d5063bee7d
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Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
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2021-06-23 15:13:56 -05:00 |
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Ross Thompson
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5de7a46237
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-06-23 09:34:42 -05:00 |
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David Harris
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718630c378
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Reduced complexity of pmpadrdec
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2021-06-23 03:03:52 -04:00 |
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David Harris
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4189b2d4a7
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Reduced complexity of pmpadrdec
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2021-06-23 02:31:50 -04:00 |
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David Harris
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1972d83002
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Refactored pmachecker to have adrdecs used in uncore
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2021-06-23 01:41:00 -04:00 |
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David Harris
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6dc54acde8
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renamed dmem to lsu and removed adrdec module from pmpadrdec
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2021-06-22 23:03:43 -04:00 |
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bbracker
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ae0fa90450
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-22 18:28:30 -04:00 |
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bbracker
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b43a8885cd
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give EBU a dedicated PMA unit as just an address decoder
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2021-06-22 18:28:08 -04:00 |
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Ross Thompson
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e7d8d0b337
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-06-22 15:47:16 -05:00 |
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Katherine Parry
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9eb6eb40bf
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rv64f FLW passes imperas tests
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2021-06-22 16:36:16 -04:00 |
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Kip Macsai-Goren
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d6c5c61b59
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Fixed mask assignment error, made usage, variables more clear
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2021-06-22 13:31:06 -04:00 |
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Kip Macsai-Goren
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b78c09baed
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Continued fixing fsm to work right with svmode
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2021-06-22 13:29:49 -04:00 |
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Kip Macsai-Goren
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852bb9296f
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updated so svmode actually causes the right state tranitions. fsm now stuck in idle loop
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2021-06-22 11:21:11 -04:00 |
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bbracker
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56b0d4d016
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added slack notifier for long sims
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2021-06-22 08:31:41 -04:00 |
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Ross Thompson
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03084a4128
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Icache now uses physical lenght bits rather than XLEN.
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2021-06-21 16:41:09 -05:00 |
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Ross Thompson
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8ec5b0c4f1
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Improved some names in icache.
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2021-06-21 16:40:37 -05:00 |
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Kip Macsai-Goren
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81b433299f
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updated mmu test pagetables so that make can be run.
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2021-06-21 12:26:47 -04:00 |
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David Harris
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82515862e3
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Commented out 100k tests to improve speed
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2021-06-21 01:43:18 -04:00 |
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David Harris
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29ad38fb9e
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Added Physical Address and Size to PMA Checker/MMU
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2021-06-21 01:27:02 -04:00 |
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David Harris
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aef408af58
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Reversed [0:...] with [...:0] in bus widths across the project
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2021-06-21 01:17:08 -04:00 |
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David Harris
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0a59b006ab
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Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals
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2021-06-20 22:59:04 -04:00 |
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