David Harris
da9f29b874
Wallypipeliendcore/soc cleanup
2023-01-14 05:57:50 -08:00
David Harris
50fae76207
csr & wally cleanup
2023-01-13 22:25:19 -08:00
Ross Thompson
4a73018d6e
Merge branch 'rastemp'
2023-01-13 18:09:50 -06:00
Ross Thompson
8e3e8591a6
Removed 1 bit from instruction classification.
2023-01-13 15:19:53 -06:00
David Harris
e67f125201
Header comments
2023-01-12 04:35:44 -08:00
David Harris
3aab0fae55
Removed unused wallypipelinedsocwrapper
2023-01-11 19:48:34 -08:00
David Harris
7d93659f6b
changed name to CORE-V-WALLY
2023-01-11 15:15:08 -08:00
David Harris
b911056e66
Changed Wally to CORE-V Wally
2023-01-11 14:03:44 -08:00
David Harris
19f0eb2aa1
Rename FP and FPU to F in signal names
2023-01-11 11:46:36 -08:00
David Harris
e6f110b953
Replaced MDUE with IntDivE in FDIVSQRT
2023-01-11 11:06:37 -08:00
David Harris
e92cffbb5e
Changed MIT license to Solderpad License
2023-01-10 11:35:20 -08:00
David Harris
9e67b9475e
Remove unused signals
2023-01-07 06:26:29 -08:00
David Harris
0a011f4548
Remove unused signals
2023-01-07 05:46:22 -08:00
Ross Thompson
e34f80db2f
More branch predictor cleanup.
2023-01-05 17:19:27 -06:00
Ross Thompson
3637067ace
Officially added global history with speculation to types of branch predictors.
2023-01-05 14:04:09 -06:00
Ross Thompson
8ca6c1255e
More branch predictor cleanup.
2023-01-05 13:36:51 -06:00
David Harris
20787964c9
Renamed muldiv to mdu
2022-12-27 19:57:10 -08:00
Ross Thompson
b5a85b55f1
Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage.
...
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
2022-12-23 15:10:37 -06:00
Ross Thompson
c8a0e7685a
DON'T USE. First commit in attempt to move fpustall detection into the decode stage.
2022-12-23 12:47:18 -06:00
Ross Thompson
6b105bd217
Renamed IFU and LSU stalls.
2022-12-22 21:56:33 -06:00
Ross Thompson
5a9e94048a
The LSU is properly using FlushW rather than TrapM.
2022-12-22 21:47:34 -06:00
Ross Thompson
cba2ed64e5
Moved privileged pc logic into privileged unit.
2022-12-20 17:55:45 -06:00
Ross Thompson
ddde82f928
Renamed FStallD to FPUStallD.
2022-12-19 09:28:45 -06:00
David Harris
da2d68c699
Use FlushE to reset integer divider FSM
2022-12-15 11:00:54 -08:00
David Harris
a8126458f6
Refactored stalls and flushes, including FDIV flush with FlushE
2022-12-15 10:56:18 -08:00
Ross Thompson
c253b882be
Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.
2022-12-15 09:53:35 -06:00
David Harris
643a2e7cf9
Use FPU divider for integer division when F is supported
2022-12-14 17:03:13 -08:00
Ross Thompson
dbc3dac03d
Removed unused flushf.
2022-12-11 16:28:11 -06:00
David Harris
3a07d56d33
Renamed FPUStallD to FCvtIntStallD
2022-12-02 11:55:23 -08:00
David Harris
db5f3c15a4
FPU divider working with execute stage stall
2022-12-02 11:11:53 -08:00
Ross Thompson
fbf543bf57
Updated HPTW to route access faults generated by the HPTW to the original access type either instruction access fault, load access fault or store access fault.
2022-11-29 17:19:31 -06:00
Ross Thompson
faa13a96e0
I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps.
2022-11-16 15:38:37 -06:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
David Harris
fde4832642
Removed unnecessary configuration conditions from subwordread sign extension/NaN boxing
2022-10-10 07:12:37 -07:00
cturek
e8a869e0e7
Added integer inputs and flags to divsqrt
2022-09-29 23:08:27 +00:00
Ross Thompson
32449dfe97
Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache.
2022-09-28 17:39:51 -05:00
Ross Thompson
996c4ca8f2
renamed ahbmulticontroller to ebu.
2022-09-26 14:37:18 -05:00
Ross Thompson
cb34b7c98f
Found the ahb burst bug.
...
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
2022-09-17 20:30:01 -05:00
Ross Thompson
cea012a640
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
89f13370e2
Removed old signals.
2022-08-31 09:50:39 -05:00
Ross Thompson
a2220fc142
Have a rough working multi manager!
2022-08-29 17:11:27 -05:00
Ross Thompson
f5584bb41c
Modified rv32e configuration to use a true ahb bus interface in the lsu and ifu.
2022-08-29 17:04:53 -05:00
Ross Thompson
233777f744
Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager.
2022-08-29 13:01:24 -05:00
David Harris
eb753b3b3f
FIxed wallypipelinedsoc merge conflict
2022-08-25 15:36:47 -07:00
David Harris
902d2067ba
Removed delayed AHB signals from top level
2022-08-25 15:34:14 -07:00
Ross Thompson
db635e3ad2
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 16:01:02 -05:00
David Harris
302a7fa294
Extended HADDR to PA_BITS
2022-08-25 13:11:36 -07:00
Ross Thompson
f67010c688
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 14:40:52 -05:00
David Harris
dda3b441d7
Continued busdp/ebu simplification
2022-08-25 10:20:02 -07:00
David Harris
19fe6d106c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-08-25 09:52:49 -07:00
