Remove unused signals

pipelined/src/ieu/controller.sv

@@ -103,7 +103,7 @@ module controller(
   logic        SubArithD;
   logic        subD, sraD, sltD, sltuD;
   logic        BranchTakenE;
-  logic        eqE, ltE, ltuE;
+  logic        eqE, ltE;
   logic        unused;
 	logic        BranchFlagE;
   logic        IEURegWriteE;

pipelined/src/ieu/datapath.sv

@@ -62,7 +62,6 @@ module datapath (
   input  logic [2:0]       ResultSrcW,
   input logic [`XLEN-1:0]  FCvtIntResW,
   input logic [`XLEN-1:0] ReadDataW,
-  // input  logic [`XLEN-1:0] PCLinkW,
   input  logic [`XLEN-1:0] CSRReadValW, MDUResultW, 
   input logic [`XLEN-1:0] FPIntDivResultW,
    // Hazard Unit signals 

pipelined/src/ieu/ieu.sv

@@ -63,7 +63,6 @@ module ieu (
   input logic [`XLEN-1:0]  FCvtIntResW,
   output logic [4:0]       RdW,
   input logic [`XLEN-1:0] ReadDataW,
-  // input  logic [`XLEN-1:0] PCLinkW,
   output logic 		   InstrValidM, 
   // hazards
   input logic 		   StallD, StallE, StallM, StallW,

pipelined/src/ifu/ifu.sv

@@ -52,7 +52,6 @@ module ifu (
 	output logic [`XLEN-1:0] 	PCE,
 	output logic 				BPPredWrongE, 
 	// Mem
-	input logic 				RetM, TrapM, 
     output logic                CommittedF, 
 	input logic [`XLEN-1:0] 	UnalignedPCNextF,
     output logic [`XLEN-1:0]    PCNext2F,
@@ -248,11 +247,9 @@ module ifu (
                                  .s({SelIROM, ~CacheableF}), .y(InstrRawF[31:0]));
     end else begin : passthrough
       assign IFUHADDR = PCPF;
-      logic CaptureEn;
       logic [31:0]  FetchBuffer;
       logic [1:0] BusRW;
       assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : '0;
-//      assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{SelIROM, SelIROM};
       assign IFUHSIZE = 3'b010;
 
       ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY), 

pipelined/src/wally/wallypipelinedcore.sv

@@ -183,7 +183,7 @@ module wallypipelinedcore (
     .BPPredWrongE, 
   
     // Mem
-    .RetM, .TrapM, .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
+    .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
     .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM,
     .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,