David Harris
468e48899a
Remove outdated code
2024-09-23 06:06:26 -07:00
Rose Thompson
32624bc6ee
Relocated a logic in a file to avoid a future merge conflict.
2024-09-05 12:50:09 -07:00
Rose Thompson
005ea52b72
Added missing signal declaration for SPI.
2024-09-05 12:20:06 -07:00
Rose Thompson
ac047a04fa
Fixed bug in SPI with the help of Naiche and Jacob. Have yet to test
...
if SPI will now run correctly with div=0 (SYSTEMCLOCK/2), but the SPI
flash card now correctly loads into the Linux OS and mount and is
reading and writting without error.
2024-09-04 17:51:48 -07:00
naichewa
3b7661dfd5
SckDiv Zero bug fixes
2024-09-03 14:58:46 -07:00
Rose Thompson
418bc6b23c
Merge branch 'main' of github.com:openhwgroup/cvw
2024-08-21 16:24:10 -07:00
Rose Thompson
faffecf891
Merge branch 'main' of github.com:openhwgroup/cvw
2024-08-21 11:02:17 -07:00
Rose Thompson
01b623b8c4
Merge branch 'main' of github.com:openhwgroup/cvw
2024-08-21 11:02:08 -07:00
Rose Thompson
f603d21826
Updated my name in multiple locations.
2024-08-21 10:50:39 -07:00
Jacob Pease
938879c5a4
Update PREADY signal to not stall during transmission on reads to read only registers.
2024-08-21 12:39:01 -05:00
Jacob Pease
b7edffdfd4
Removed now inaccurate comments.
2024-08-20 16:38:15 -05:00
Jacob Pease
f960662e93
Removed now inaccurate comments.
2024-08-20 16:38:15 -05:00
Jacob Pease
d8b75440b6
With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.
2024-08-20 16:24:37 -05:00
Jacob Pease
baad4e0fd2
With Naiche's help, we fixed the SPI controllers clock polarity and phase settings. Added conditions to the SPI regression tests.
2024-08-20 16:24:37 -05:00
Jacob Pease
43b17b5058
Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose.
2024-08-20 14:40:50 -05:00
Jacob Pease
9ac889e3e8
Update SPI peripheral to accept writes to FIFO always. Worked on this together with Naiche and Rose.
2024-08-20 14:40:50 -05:00
David Harris
8e62c578ea
Detect illegal writes to URO HPM counters
2024-08-15 10:43:20 -07:00
David Harris
e5d262063f
Detect illegal writes to URO HPM counters
2024-08-15 10:43:20 -07:00
David Harris
f0f0e96eee
Fixes mstatus.FS to also be set when a FP operation sets a floating-point flag even if it doesnt write a FP register
2024-08-13 07:34:58 -07:00
David Harris
125884eb74
Fixes mstatus.FS to also be set when a FP operation sets a floating-point flag even if it doesnt write a FP register
2024-08-13 07:34:58 -07:00
David Harris
ca82a63de6
Fixed c.slli hint discovered by Lee (Issue 910)
2024-08-13 06:45:45 -07:00
David Harris
705ee60618
Fixed c.slli hint discovered by Lee (Issue 910)
2024-08-13 06:45:45 -07:00
David Harris
64709bccab
Fixed fldsp decompress with rd = 0
2024-08-08 21:45:57 -07:00
David Harris
b334dc50a4
Fixed fldsp decompress with rd = 0
2024-08-08 21:45:57 -07:00
David Harris
010038ec32
Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED
2024-08-08 05:27:35 -07:00
David Harris
fa98ae8c30
Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED
2024-08-08 05:27:35 -07:00
Jacob Pease
f8f16d2d34
Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv
2024-08-06 17:36:42 -05:00
Jacob Pease
2dc7e0f76f
Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv
2024-08-06 17:36:42 -05:00
Jacob Pease
11ca2567b8
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-08-06 17:09:39 -05:00
Jacob Pease
af2344d2d5
Merge branch 'main' of github.com:openhwgroup/cvw into spiboot
2024-08-06 17:09:39 -05:00
Jacob Pease
bd07a60c07
Updated wally source files for zsbl testing.
2024-08-02 15:33:57 -05:00
Jacob Pease
11a057b0b3
Updated wally source files for zsbl testing.
2024-08-02 15:33:57 -05:00
Jacob Pease
2ed0b239e8
Added preload pointing to data.mem in ram1p1rwbe.sv
2024-08-02 15:21:15 -05:00
Jacob Pease
1e20d5aea6
Added preload pointing to data.mem in ram1p1rwbe.sv
2024-08-02 15:21:15 -05:00
Rose Thompson
2e4ca4c876
Merge pull request #895 from davidharrishmc/dev
...
Fix Issue 894 about floating-point decoding of reserved rm/frm
2024-07-25 11:51:32 -05:00
Rose Thompson
6496454054
Merge pull request #895 from davidharrishmc/dev
...
Fix Issue 894 about floating-point decoding of reserved rm/frm
2024-07-25 11:51:32 -05:00
David Harris
7360be1234
Legalized PMPconfig WARL
2024-07-25 09:43:54 -07:00
David Harris
faa1378920
Legalized PMPconfig WARL
2024-07-25 09:43:54 -07:00
David Harris
c637e40058
CHeck legal rnum field when decoding aes64ks1i
2024-07-25 09:19:23 -07:00
David Harris
d5af25ffbf
CHeck legal rnum field when decoding aes64ks1i
2024-07-25 09:19:23 -07:00
Jacob Pease
6fc10adc25
Added ability to split boot.memfile into boot.mem and data.mem.
2024-07-25 11:19:15 -05:00
Jacob Pease
336a413f31
Added ability to split boot.memfile into boot.mem and data.mem.
2024-07-25 11:19:15 -05:00
David Harris
7234abebef
Issue #894 : trap on floating-point ops with reserved rounding modes: detect Zfa flt
2024-07-25 09:09:13 -07:00
David Harris
5bf7250687
Issue #894 : trap on floating-point ops with reserved rounding modes: detect Zfa flt
2024-07-25 09:09:13 -07:00
David Harris
337e40ac1b
Issue #894 : trap on floating-point ops with reserved rounding modes
2024-07-25 06:59:58 -07:00
David Harris
f7dd49cc6c
Issue #894 : trap on floating-point ops with reserved rounding modes
2024-07-25 06:59:58 -07:00
Rose Thompson
c11036358a
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Rose Thompson
b1a711ae0f
Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
2024-07-24 12:47:50 -05:00
Rose Thompson
7960f26e84
Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.
2024-07-23 17:44:37 -05:00
Rose Thompson
9404a339ee
Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.
2024-07-23 17:44:37 -05:00
