James E. Stine
752552970c
Add some example wavedrom files - more on the way including ppt
2021-02-04 14:41:42 -06:00
Thomas Fleming
8d7a515ae7
Complete STORE tests
2021-02-04 15:38:22 -05:00
Noah Boorstin
fc734eb14e
busybear: add more CSRs
2021-02-04 20:13:36 +00:00
Noah Boorstin
77a88d8019
busybear: check initial values also
2021-02-04 19:22:09 +00:00
Brett Mathis
11e2666bb2
Parallel FSR's and F CTRL logic
2021-02-04 02:25:55 -06:00
Jarred Allen
088fbbcbf0
Change busybear test to use work-busybear library
2021-02-03 11:12:47 -05:00
Jarred Allen
f700efc2b3
Start on a test set for loads
2021-02-03 00:37:43 -05:00
David Harris
2a80bcf543
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-02 19:44:43 -05:00
David Harris
756352f129
Minor tweaks
2021-02-02 19:44:37 -05:00
Jarred Allen
e5bd749e2a
Refactor regression test
2021-02-02 17:22:29 -05:00
Noah Boorstin
d2064987e9
Add busybear testbench to nightly regression checking
...
If you don't like how I did this please feel free to undo it
2021-02-02 22:05:35 +00:00
Noah Boorstin
b5f474d9f5
same thing but do that right this time
2021-02-02 21:47:15 +00:00
Noah Boorstin
6dd5c42d55
change undefined syntax in extend.sv
...
don't need verilator execption anymore
2021-02-02 21:39:20 +00:00
David Harris
429f48e766
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
9f9c3bcece
Changed DTIM latency to 2 cycles
2021-02-02 14:22:12 -05:00
David Harris
616830a3f0
Cleaned up hazard interface
2021-02-02 13:53:13 -05:00
David Harris
587a343dac
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-02-02 13:42:35 -05:00
David Harris
229bde5953
Moved LoadStall generation to IEU
2021-02-02 13:42:23 -05:00
David Harris
bb83fda1d8
Moved writeback pipeline registers from datapth into DMEM and CSR
2021-02-02 13:02:31 -05:00
Jarred Allen
da43b2be53
Fix intermittent errors caused by weird library stuff
2021-02-02 11:20:09 -05:00
Jarred Allen
b57604f4e4
Add the regression logs and new regression byproducts to the gitignore
2021-02-02 10:43:41 -05:00
Noah Boorstin
f1768ee50b
Busybear: start checking CSRs
...
scounteren and mcounteren are currenly manually deleted from the CSRs list
(see slack channl #linux-bringup)
and 3 of the CSRs referenced are skipped because of weird locations for them
oh and this doesn't check their initial state, just their changing. This could be a problem
2021-02-02 06:06:03 +00:00
David Harris
92bf1674b4
Moved fpu to temporary location to fix compile and cleaned up interface formatting
2021-02-01 23:44:41 -05:00
Jarred Allen
f143518b23
Fix issues in parallel regression testing
2021-02-01 23:29:03 -05:00
Noah Boorstin
38265c03b7
busybear: start adding CSR checking
...
@kaveh is there a less verbose way to do this?
2021-02-01 22:08:51 -05:00
Brett Mathis
bcb722272e
OSU FPU IP initial commit
2021-02-01 19:33:43 -06:00
Noah Boorstin
d592db79c9
busybear: change register file checking to only store register changed
...
this should make parsedRegs.txt much smaller
2021-02-02 01:27:43 +00:00
Noah Boorstin
71f5bb0ce8
Add PCW checking
...
for now, doesn't check InstrW because it fails on compressed instructions
2021-02-01 23:57:33 +00:00
David Harris
1a3963bed0
Renamed DCU to DMEM
2021-02-01 18:52:22 -05:00
Jarred Allen
5cf3d188c6
Parallelize regression-wally.p
2021-02-01 15:40:27 -05:00
Noah Boorstin
1b9ec8b339
busybear: print warning when NOPing out instructions
2021-02-01 19:44:56 +00:00
Noah Boorstin
a82f8977c6
busybear: NOP out floating point instructions for now
...
Why does linux even try to do float stuff doing booting??
also, now runs the first 100k instructions!
2021-01-30 19:52:47 +00:00
Noah Boorstin
cca60ed06d
update busybear testbench to conform to new structure
...
aaaaaaaaaaaaaaaaaahhhh so many changes
also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
2021-01-30 19:19:00 +00:00
David Harris
07af481b67
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
David Harris
29313a108b
Working on reading instruction from TIM
2021-01-30 01:57:51 -05:00
David Harris
5429424871
Adding stalls for memory delays
2021-01-30 01:43:49 -05:00
David Harris
26c560fba3
Added HCLK and HRESETn
2021-01-30 00:56:12 -05:00
David Harris
9511dcac84
Connected AHB bus to Uncore
2021-01-29 23:43:48 -05:00
David Harris
9297376873
Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team
2021-01-29 18:06:36 -05:00
David Harris
6c76962847
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 17:29:01 -05:00
David Harris
9530039e3d
Implemented adrdec for uncore
2021-01-29 17:28:53 -05:00
Teo Ene
5e5e03c717
- Removed latch on CSRCReadValM in csrc.sv
...
- Changed top level to wallypipelinedhart
2021-01-29 15:56:51 -06:00
Teo Ene
f69b84fe31
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-01-29 15:04:51 -06:00
Teo Ene
af5a068b5d
Synth automatically globs all available verilog files now, instead of requiring manual file listing
2021-01-29 15:04:43 -06:00
David Harris
6d5b01357d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 15:38:01 -05:00
David Harris
d104e5a4be
Moving data memory to uncore
2021-01-29 15:37:51 -05:00
Teo Ene
f0bbd71874
Added AHBW to rv32ic config file as well
2021-01-29 12:29:08 -06:00
Noah Boorstin
7183910c84
update busybear testbench to conform to new structure
2021-01-29 17:46:50 +00:00
David Harris
4687d6998a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-01-29 01:07:22 -05:00
David Harris
e4e95bf941
Added ahblite bus interface unit
2021-01-29 01:07:17 -05:00
