183 Commits

Author	SHA1	Message	Date
Ross Thompson	c2cf3f9fb6	Updating the test bench to include a function radix. Not done.	2021-02-26 19:43:40 -06:00
David Harris	73920282af	Eliminated flushing pipeline on CSR reads	2021-02-26 17:00:07 -05:00
David Harris	cd4ba8831c	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	38b8cc652c	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
David Harris	7737b0f709	Fixed fetch stall after jump in bus unit	2021-02-23 09:08:57 -05:00
David Harris	f372e2b8e8	Debugging Bus interface	2021-02-22 13:48:30 -05:00
Ross Thompson	7d6093b302	Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. ... About 149307ns of simulation run.	2021-02-18 21:32:15 -06:00
David Harris	a7dd20b388	Multiply instructions working	2021-02-17 15:29:20 -05:00
David Harris	adc5d5bc1a	Added MUL	2021-02-15 22:27:35 -05:00
Domenico Ottolia	3ee975dd5a	Add privileged test cases	2021-02-14 17:01:46 -05:00
Shreya Sanghai	4e887f83a3	added branch tests	2021-02-12 22:40:08 -05:00
Tejus Rao	fb6a4bbbf0	added test cases for ADDW, SUBW, SLLW, SRLW, SRAW	2021-02-11 13:38:38 -05:00
ethan-falicov	7925fe3131	Fixed merge conflict stuff	2021-02-10 10:03:30 -05:00
ethan-falicov	06517631cc	More merge conflicts yay	2021-02-10 09:54:30 -05:00
ethan-falicov	863796b3c1	Merge conflict fixing	2021-02-10 09:45:47 -05:00
ethan-falicov	67662b888e	Adding I Type test cases from Lab 1	2021-02-10 09:39:43 -05:00
David Harris	b121b90b28	Debugging bus interface.	2021-02-10 01:43:54 -05:00
David Harris	842c374de9	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
Jarred Allen	e334475ab5	Fix compile error in imperas testbench	2021-02-07 15:48:12 -05:00
Elizabeth Hedenberg	805817cda4	merge conflict?	2021-02-07 02:34:49 -05:00
Jarred Allen	29b7a0cd25	Actually run the WALLY-LOAD tests	2021-02-06 14:56:40 -05:00
bbracker	15c0b4af22	JAL testing	2021-02-05 08:08:42 -05:00
Thomas Fleming	8d7a515ae7	Complete STORE tests	2021-02-04 15:38:22 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00
David Harris	26c560fba3	Added HCLK and HRESETn	2021-01-30 00:56:12 -05:00
David Harris	9511dcac84	Connected AHB bus to Uncore	2021-01-29 23:43:48 -05:00
David Harris	d104e5a4be	Moving data memory to uncore	2021-01-29 15:37:51 -05:00
David Harris	e4e95bf941	Added ahblite bus interface unit	2021-01-29 01:07:17 -05:00
David Harris	37a58cea17	Repartitioned with Instruction Fetch Unit, Integer Execution Unit	2021-01-27 22:49:47 -05:00
David Harris	db5f45c240	Moved privileged unit from datapath to hart	2021-01-27 07:46:52 -05:00
David Harris	4318629b32	Repartitioned datapath and controller into ieu	2021-01-27 06:40:26 -05:00
David Harris	bf07ec92b5	Added test configurations	2021-01-25 11:28:43 -05:00