Github_Repos/cvw
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8,977 Commits 4 Branches 2 Tags 53 MiB
3fde6c13f7
Commit Graph

258 Commits

Author SHA1 Message Date
Jacob Pease
3fde6c13f7 Added functions to read registers and print information on failure. Also added a getTime function for a pretty boot display. 2024-08-02 15:14:30 -05:00
Jacob Pease
906fa73747 Updated formatting of gpt.c and boot.c. 2024-07-31 11:12:05 -05:00
Jacob Pease
0396181d1e Added function to set SPI clock speed. 2024-07-31 11:00:44 -05:00
Jacob Pease
826576bfc7 Cleaned up code formatting a bit and added ability to set the SD card clock speed. 2024-07-31 10:59:41 -05:00
Jacob Pease
5d6699dc4c Added extra UART macros and functions for code readability and the ability to print decimal numbers. 2024-07-31 10:58:15 -05:00
Jacob Pease
8a5898ebc1 Added carriage returns to line feed characters. UART messages print properly now. 2024-07-25 13:05:57 -05:00
Jacob Pease
f12319ca96 Changed formatting and added new UART divsor calculation from OpenSBI. 2024-07-25 13:04:27 -05:00
Jacob Pease
6fc10adc25 Added ability to split boot.memfile into boot.mem and data.mem. 2024-07-25 11:19:15 -05:00
Jacob Pease
02bb9b0b8b Fixed SDCCLK name discrepency. 2024-07-24 22:48:31 -05:00
Jacob Pease
a34836c08b Commented out references to old axi IP from wally.tcl. 2024-07-24 22:47:15 -05:00
Jacob Pease
ffec8cfb20 Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram. 2024-07-24 22:46:24 -05:00
Jacob Pease
36d330a173 Masked lower byte when writing to DLL. 2024-07-24 22:44:27 -05:00
Jacob Pease
a97c7f0b58 Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future 2024-07-24 22:43:47 -05:00
Jacob Pease
e175a41863 Added uart header to gpt.c. 2024-07-24 22:43:16 -05:00
Jacob Pease
c18b3d814d Fixed verilog bugs. 2024-07-23 17:26:39 -05:00
Jacob Pease
23d9c7a486 Fixed syntax bugs. inline functions are now static and in the spi.h header. 2024-07-23 17:00:32 -05:00
Jacob Pease
692bbc35fd Initial pass on SPI based bootloader code finished. 2024-07-23 16:33:49 -05:00
Jacob Pease
659f0d3646 Added some minor error checking to gpt.c. 2024-07-23 16:32:52 -05:00
Jacob Pease
fe0f6de2ab Added sd_read64 to help with block reads and crc checking. 2024-07-23 16:32:29 -05:00
Jacob Pease
a95106b516 Progress made on implementing new disk read function. 2024-07-23 15:47:23 -05:00
Jacob Pease
db13ed63b9 Removed references to card_type. 2024-07-23 15:46:18 -05:00
Jacob Pease
188df61037 Added uart print functions and the Wally banner. SD card can now be initialized. Removed old code from boot.c 2024-07-23 14:18:42 -05:00
Jacob Pease
ef1f55626c Added sd_cmd and utility SPI functions. 2024-07-22 16:57:04 -05:00
Jacob Pease
4585ad8891 Added new SDC clock constraint. 2024-07-22 13:05:16 -05:00
Jacob Pease
a722c3c0a1 Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP. 2024-07-22 12:36:39 -05:00
Jacob Pease
b6fac581f7 Corrected the CRC7 code with the right sequence of instructions. 2024-07-22 01:19:10 -05:00
Jacob Pease
cc32e90f66 Added inital spi based sd card code. Working on CRC7 code that works. 2024-07-20 14:00:43 -05:00
Jacob Pease
6018ab82ab Added tentative spi_send_byte function. 2024-07-19 12:30:32 -05:00
Jacob Pease
5123a43ba2 Added initial spi code to fpga/zsbl 2024-07-19 11:35:12 -05:00
Ross Thompson
ab1ee3d69b Removed *** from IFU, lrcs. 2024-06-19 09:40:35 -07:00
Ross Thompson
c5dac4d775 Removed *** from fpga top. 2024-06-19 09:28:21 -07:00
Jacob Pease
7a417d7a6c Added true bootloader to fpga/zsbl directory. 2024-05-31 15:28:25 -05:00
Jacob Pease
3f7659c8ad Removed old fpgaTop.v file. 2024-05-30 16:15:19 -05:00
Jacob Pease
7ecd1c7d5f The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file. 2024-05-30 15:48:27 -05:00
Rose Thompson
8123695831 Maded insert_debug_comment.sh compatible with cygwin. 2024-04-22 10:48:34 -05:00
Rose Thompson
3bed733301 Fixed fpga to work with the updated regression changes. 2024-04-22 10:42:01 -05:00
Rose Thompson
c1221e6608 Fixed insert_debug_comment.sh to work with the older version of bash. 2024-04-16 10:55:26 -05:00
Rose Thompson
6097444b5a Added missing file for compiling the fpga zero stage bootloader. 2024-04-11 10:30:56 -05:00
Rose Thompson
60f96112db Moved the zero stage boot loader to the fpga directory. 2024-03-01 10:23:55 -06:00
Rose Thompson
cc7f433ce0 Update the fpga scripts to use the new derivative configs. 2024-01-31 13:19:28 -06:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
Rose Thompson
7693c5d4e2 Updates to fpga top level. 2023-12-15 15:32:05 -06:00
Rose Thompson
26cd22c388 Replaced fpga's verilog top with system verilog. 2023-12-15 13:42:52 -06:00
Rose Thompson
dab9d7ab3c Replaced fpga top level verilog with system verilog. 2023-12-15 13:07:08 -06:00
Rose Thompson
34631c54d3 Get's the fpga building again after the git history rewrite. 2023-12-14 17:08:25 -06:00
Jacob Pease
7e494f2d3b Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile. 2023-12-01 18:59:18 -06:00
Jacob Pease
71066cae12 Modified FPGA Makefile to override with relative path. FPGA boots now. 2023-11-30 17:51:15 -06:00
Rose Thompson
b137759b45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-11-20 10:34:36 -06:00
Rose Thompson
cdd21d6635 Added menvcfg to debugger for checking what linux has configured. 2023-11-19 13:44:22 -06:00
Jacob Pease
87e6a5ccf2 Updated ROM to preload bootloader from file and infer a block ram when building for FPGA. 2023-11-18 19:15:39 -06:00