Ross Thompson
b8572d6a2a
Changed several things.
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Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Ross Thompson
f7583d0e0d
Updated uncore to use sdc.
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Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
2021-10-25 14:07:44 -05:00
Ross Thompson
6bad4058eb
Merge branch 'main' into fpga
2021-10-22 16:09:16 -05:00
Katherine Parry
00cc1e0c5c
put the FMA priority encoders into their own module
2021-10-22 10:03:12 -07:00
Ross Thompson
09dc3e1143
Merge branch 'main' into fpga
2021-10-20 16:24:55 -05:00
David Harris
4aeadaacf0
moved coemark and testsBP to tests
2021-10-20 09:10:06 -07:00
Ross Thompson
77a89c30de
Fixed bug with the external memory region selection.
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Updated bios program to copy just 127MB to dram.
2021-10-19 11:23:23 -05:00
David Harris
47f7a5db9c
Fixed multiplier and pointed arch tests to new path in addins
2021-10-18 15:43:59 -07:00
James E. Stine
6b30adb309
Clean up some signals - beautification onging
2021-10-14 17:12:00 -05:00
Kip Macsai-Goren
ffcf5f5825
Fixed typo in imperas64mmu tests causing PMP tests not to run.
2021-10-14 13:42:24 -07:00
James E. Stine
eb64a7f0c9
Update to fpdivsqrt to go on posedge as it should. Also an update to
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individual regression test for TestFloat (still needs some tweaking)
2021-10-13 17:14:42 -05:00
bbracker
886a650da4
change infrastructure to expect only 6.3 million from buildroot
2021-10-12 10:41:15 -07:00
Ross Thompson
5fdac9fa3b
Merge branch 'main' into fpga
2021-10-11 18:17:58 -05:00
Ross Thompson
3d9d4cc03f
Partially working sd card reader.
2021-10-11 10:23:45 -05:00
David Harris
a077735ecc
Major reorganization of regression and simulation and testbenches
2021-10-10 15:07:51 -07:00
James E. Stine
11cf3d97c5
Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH
2021-10-10 15:44:01 -05:00
bbracker
5a987cf0ca
use correct string formatting function
2021-10-10 10:09:59 -07:00
bbracker
54e0e8eb5b
make testbench-linux halt on some discrepancies with QEMUw
2021-10-09 17:22:30 -07:00
Kip Macsai-Goren
381a8fcd27
updated pmp output to correspond to test changes, commented out execute tests until cache/fence interaction works fully.
2021-10-08 15:40:18 -07:00
David Harris
7e340d16fd
moved fp vectors into vectors subdirectory
2021-10-07 23:28:06 -04:00
David Harris
626780381a
Included TestFloat and SoftFloat
2021-10-07 23:03:45 -04:00
James E. Stine
0c408a9816
update scripts
2021-10-07 15:14:54 -05:00
James E. Stine
4dcfcfacfc
TV for conversion and compare
2021-10-06 14:38:32 -05:00
James E. Stine
658dcc8c1b
Update to testbench for FP stuff
2021-10-06 13:16:38 -05:00
James E. Stine
4ece7b5341
Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included
2021-10-06 08:56:01 -05:00
Skylar Litz
a924e79e26
added delayed MIP signal
2021-10-04 18:23:31 -04:00
Ross Thompson
c10261f0ad
Added more debug flags.
2021-10-03 11:41:21 -05:00
David Harris
bf0061be66
Reduced cycle count for DIVW/DIVUW by two
2021-10-03 09:42:22 -04:00
David Harris
30ec68d567
Parameterized number of bits per cycle for integer division
2021-10-03 01:10:15 -04:00
David Harris
73d852b1ef
Divide performs 2 steps per cycle
2021-10-02 09:19:25 -04:00
David Harris
35e5a5cef3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 23:15:34 -04:00
bbracker
5022647041
Revert "first attempt at verilog side of checkpoint functionality"
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This reverts commit f6ef8e5656
2021-09-30 20:45:26 -04:00
David Harris
a39e14663d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 20:07:43 -04:00
Ross Thompson
ec4a07de64
Movied tristate to test bench level.
2021-09-30 11:27:42 -05:00
Ross Thompson
db18aac9af
Partially sd card read on fpga.
2021-09-30 11:23:09 -05:00
David Harris
e1ad732178
SRT Division unsigned passing Imperas tests
2021-09-30 12:17:24 -04:00
bbracker
f6ef8e5656
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
Ross Thompson
99070127d8
Added debugging directives to system verilog.
2021-09-27 13:57:46 -05:00
bbracker
2ffdbdf6d2
condense testbench code; debug_level of 0 means don't check at all
2021-09-27 03:03:11 -04:00
Ross Thompson
f2c1ca4bd5
added support to due partial fpga simulation.
2021-09-26 15:00:00 -05:00
Ross Thompson
6ac96db20b
Merge branch 'main' into fpga
2021-09-26 13:22:53 -05:00
Ross Thompson
5bdd6a9d0c
Almost done writting driver for flash card reader.
2021-09-25 19:05:07 -05:00
Ross Thompson
3a15cc7872
We now have a rough sdc read routine.
2021-09-25 17:51:38 -05:00
Ross Thompson
232d4a554f
Have program which checks for sdc init and issues read, but read done is
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not correctly being read back by the software. The error is in how the
sdc indicates busy.
2021-09-24 15:53:38 -05:00
Ross Thompson
0f87f68b9d
Added either the sdModel or constant driver for the SDC ports in all test benches.
2021-09-24 12:31:51 -05:00
Ross Thompson
0a33f5fa46
setup so the sdc does not need to load a model in the imperas test bench.
2021-09-24 11:30:52 -05:00
Ross Thompson
78028947bf
Updated Imperas test bench to work with the SDC reader.
2021-09-24 11:22:54 -05:00
bbracker
441759b81c
switch testbench-linux's interrupts from xcause to mip and improve warning messages
2021-09-22 12:33:11 -04:00
bbracker
b1be8f4858
fix regression
2021-09-15 17:30:59 -04:00
David Harris
e32ab128e9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-13 12:41:07 -04:00
