David Harris
3a2b459439
Merged coremark changes
2022-01-10 05:09:28 +00:00
David Harris
401a5b1779
Removed unused coremark_bare
2022-01-10 05:05:55 +00:00
David Harris
39d5570d2c
Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
2022-01-10 05:04:13 +00:00
Ross Thompson
73c488914f
Added icache access and icache miss to performance counters.
2022-01-09 22:56:56 -06:00
Ross Thompson
04ea93aa27
Added performance counters to wavefile.
2022-01-09 22:42:14 -06:00
Ross Thompson
ae927e2bc6
Fixed wavefile.
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Converted coremark to use elf2hex.
2022-01-09 22:03:10 -06:00
Kip Macsai-Goren
54aab6cdde
comment cleanup
2022-01-09 18:16:42 +00:00
Kip Macsai-Goren
53ea1360ce
updated PMA tests, everything passes except successful writes to protected regions.
2022-01-09 18:16:00 +00:00
Kip Macsai-Goren
5f7323f25f
changed test case types to lookup table instead of beq's
2022-01-09 16:56:37 +00:00
David Harris
0212260eef
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-09 14:39:33 +00:00
David Harris
c1d2199dc6
Fixed RISCV path in coremark Makefile
2022-01-09 14:39:22 +00:00
Ross Thompson
d14dffd010
Updated debug constraints again to match changes in verilog.
2022-01-08 13:28:51 -06:00
Ross Thompson
0f14d2ec88
Added advanced Vivado debug scripts.
2022-01-07 17:56:40 -06:00
Ross Thompson
509a0cd3f8
Fixed bug with interlock fsm. The interlock fsm should suppress bus and cache requests by the cpu
...
only at the start of a request. Pending interrupt was used to start one of these suppressions;
however because of the way the cache's fsm was separated from the bus fsm, the cache now made requests
to the bus fsm. On a miss with write back, the inital fetch is handled correctly. However if an
interrupt becam pending then the the next request (eviction) made by the cache was also suppressed.
This keeps the d cache fsm stuck in the STATE_MISS_EVICT_DIRTY state as it think it has made a request
to the bus fsm, but the pending interrupt ignored the request.
The solution is to modify how cpu requests are suppressed. Instead of relying on pending interrupt
it is better to use interrupt which will be disabled if the dcache is currently processing the evict.
2022-01-07 17:55:34 -06:00
David Harris
54d852f6ae
renamed regression-wally.py to regression-wally
2022-01-07 17:47:38 +00:00
David Harris
bea6d0856d
Testbench directory cleanup
2022-01-07 17:02:16 +00:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
David Harris
fedb9d3287
moved proposed-sdc
2022-01-07 12:44:21 +00:00
David Harris
40af3abef9
piplined directory cleanup
2022-01-07 12:43:50 +00:00
David Harris
c97572d209
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-07 05:39:16 +00:00
Ross Thompson
c8d47fc7c3
Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
...
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
David Harris
2a64b1bc95
Used .* in wrapper
2022-01-07 05:23:42 +00:00
Ross Thompson
0fddceffa6
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
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assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
David Harris
1d8451c2cf
Capitalized LSU and IFU, changed MulDiv to MDU
2022-01-07 04:30:00 +00:00
David Harris
0e023e29d8
Code cleanup
2022-01-07 04:07:04 +00:00
Ross Thompson
c9c3bddc6d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 17:19:20 -06:00
Ross Thompson
008ac20a43
Minor optimization to cache replacement.
2022-01-06 17:19:14 -06:00
David Harris
08231d4e66
Tests cleanup:
2022-01-06 23:07:22 +00:00
David Harris
cb68548b88
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 23:04:33 +00:00
David Harris
fc4db84bbc
Makefile make allclean
2022-01-06 23:04:30 +00:00
David Harris
e5f9fbb238
Fixed multiplier nan boxing bug
2022-01-06 23:03:29 +00:00
Katherine Parry
b3ebce0365
some FPU test fixes
2022-01-06 23:03:20 +00:00
Ross Thompson
e1db967417
Clean up of cachefsm.
2022-01-06 16:32:49 -06:00
David Harris
1c96b22b8f
More FP unpacking fix
2022-01-06 22:22:22 +00:00
David Harris
340752616d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 21:45:20 +00:00
David Harris
2b8e8707a7
Floating point test cleanup
2022-01-06 21:45:16 +00:00
Ross Thompson
4a93c0e512
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 15:18:27 -06:00
Ross Thompson
6bd447d570
Patched the ILA's debug2.xdc constraint file to work with the wally memory design.
2022-01-06 15:18:18 -06:00
David Harris
2b4c81fe98
Fixed unpacking bug; regression runs again
2022-01-06 18:22:30 +00:00
David Harris
55e757db03
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-06 18:10:32 +00:00
David Harris
c9aa21d5a3
FPU debug and configurable logic cleanup
2022-01-06 18:10:25 +00:00
Ross Thompson
8c71daff11
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 11:56:23 -06:00
Ross Thompson
42623141cd
Updated fpga ILA constraints to match the new changes to the rtl.
2022-01-06 11:56:09 -06:00
Ross Thompson
7f66177769
Fixed bug in synthesis script.
2022-01-05 23:07:36 -06:00
Ross Thompson
d30ad136f3
cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.
2022-01-05 22:56:18 -06:00
Ross Thompson
365b2715ed
More name cleanup in cache.
2022-01-05 22:37:53 -06:00
Ross Thompson
77efcad15b
Changed names of address in caches.
...
Removed old cache files.
2022-01-05 22:19:36 -06:00
Ross Thompson
5a2ae561a7
Updates to support fpga.
2022-01-05 18:07:23 -06:00
Ross Thompson
3517db6b64
Fixed xilinx synth error with $error in extend.sv
2022-01-05 17:48:08 -06:00
Kip Macsai-Goren
1556fb967d
fixed 32 vs 64 bit copying error
2022-01-05 23:14:12 +00:00
