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Configurable RISC-V Processor
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Ross Thompson 0fddceffa6 Modified the mmu to not mux the lower 12 bits of the physical address and instead directly 
assign from the input non translated virtual address.  Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address.  This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
addins some FPU test fixes 2022-01-06 23:03:20 +00:00
benchmarks/riscv-coremark Added file showing how to compile riscv toolchain for different extension combinations. 2021-12-19 20:31:55 -06:00
bin Replaced exe2memfile with SiFive elf2hex 2022-01-05 22:10:26 +00:00
examples Fixed unpacking bug; regression runs again 2022-01-06 18:22:30 +00:00
fpga Patched the ILA's debug2.xdc constraint file to work with the wally memory design. 2022-01-06 15:18:18 -06:00
pipelined Modified the mmu to not mux the lower 12 bits of the physical address and instead directly 2022-01-06 23:19:09 -06:00
tests Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-06 18:10:32 +00:00
.gitattributes Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
.gitignore Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
.gitmodules .gitmodule added dirty riscv-arch-test 2021-12-29 23:50:17 +00:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
Makefile Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
README.md Update README.md 2022-01-05 11:29:54 -08:00
setup.sh Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wallyVirtIO.patch added wallyVirtIO.patch from Ross 2021-12-22 07:04:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor

Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.

See Chapter 2 of draft book of how to install and compile tests.