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More name cleanup in cache.

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This commit is contained in:
Ross Thompson 2022-01-05 22:37:53 -06:00
parent 77efcad15b
commit 365b2715ed
2 changed files with 50 additions and 52 deletions
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76
pipelined/src/cache/cache.sv vendored
View File

@ -26,42 +26,40 @@
`include "wally-config.vh"
module cache #(parameter integer LINELEN,
parameter integer NUMLINES,
parameter integer NUMWAYS,
parameter integer NUMLINES,
parameter integer NUMWAYS,
parameter integer DCACHE = 1)
(input logic clk,
input logic reset,
input logic CPUBusy,
// cpu side
input logic CPUBusy,
input logic [1:0] RW,
input logic [1:0] Atomic,
input logic FlushCache,
input logic InvalidateCacheM,
input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits.
input logic [`PA_BITS-1:0] PAdr, // physical address
input logic [11:0] NoTranAdr, // physical or virtual address
input logic [`XLEN-1:0] FinalWriteData,
output logic [`XLEN-1:0] ReadDataWord,
output logic CacheCommitted,
// Bus fsm interface
input logic IgnoreRequest,
output logic CacheFetchLine,
output logic CacheWriteLine,
input logic CacheBusAck,
output logic [`PA_BITS-1:0] CacheBusAdr,
input logic [LINELEN-1:0] CacheMemWriteData,
output logic [`XLEN-1:0] ReadDataLineSets [(LINELEN/`XLEN)-1:0],
output logic CacheCommitted,
output logic CacheStall,
// to performance counters
// to performance counters to cpu
output logic CacheMiss,
output logic CacheAccess,
input logic InvalidateCacheM
);
// lsu control
input logic IgnoreRequest,
// Bus fsm interface
output logic CacheFetchLine,
output logic CacheWriteLine,
input logic CacheBusAck,
output logic [`PA_BITS-1:0] CacheBusAdr,
input logic [LINELEN-1:0] CacheMemWriteData,
output logic [`XLEN-1:0] ReadDataLineSets [(LINELEN/`XLEN)-1:0]);
localparam integer LINEBYTELEN = LINELEN/8;
@ -82,12 +80,12 @@ module cache #(parameter integer LINELEN,
logic [LINELEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0];
logic [NUMWAYS-1:0] WayHit;
logic CacheHit;
logic [LINELEN-1:0] ReadDataLineM;
logic [LINELEN-1:0] ReadDataLine;
logic [WORDSPERLINE-1:0] SRAMWordEnable;
logic SRAMWordWriteEnableM;
logic SRAMLineWriteEnableM;
logic [NUMWAYS-1:0] SRAMLineWayWriteEnableM;
logic SRAMWordWriteEnable;
logic SRAMLineWriteEnable;
logic [NUMWAYS-1:0] SRAMLineWayWriteEnable;
logic [NUMWAYS-1:0] SRAMWayWriteEnable;
@ -95,7 +93,7 @@ module cache #(parameter integer LINELEN,
logic [NUMWAYS-1:0] VictimDirtyWay;
logic VictimDirty;
logic [2**LOGWPL-1:0] MemPAdrDecodedW;
logic [2**LOGWPL-1:0] MemPAdrDecoded;
logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
logic [TAGLEN-1:0] VictimTag;
@ -136,7 +134,7 @@ module cache #(parameter integer LINELEN,
.WriteEnable(SRAMWayWriteEnable),
.VDWriteEnable(VDWriteEnableWay),
.WriteWordEnable(SRAMWordEnable),
.TagWriteEnable(SRAMLineWayWriteEnableM),
.TagWriteEnable(SRAMLineWayWriteEnable),
.WriteData(SRAMWriteData),
.SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict,
.VictimWay, .FlushWay, .SelFlush,
@ -163,7 +161,7 @@ module cache #(parameter integer LINELEN,
// ReadDataLineWayMaskedM is a 2d array of cache line len by number of ways.
// Need to OR together each way in a bitwise manner.
// Final part of the AO Mux. First is the AND in the cacheway.
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLineM));
or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLine));
or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag));
@ -173,7 +171,7 @@ module cache #(parameter integer LINELEN,
genvar index;
if(DCACHE == 1) begin: readdata
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
assign ReadDataLineSets[index] = ReadDataLineM[((index+1)*`XLEN)-1: (index*`XLEN)];
assign ReadDataLineSets[index] = ReadDataLine[((index+1)*`XLEN)-1: (index*`XLEN)];
end
// variable input mux
assign ReadDataWord = ReadDataLineSets[PAdr[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]];
@ -181,8 +179,8 @@ module cache #(parameter integer LINELEN,
logic [31:0] ReadLineSetsF [LINELEN/16-1:0];
logic [31:0] FinalInstrRawF;
for(index = 0; index < LINELEN / 16 - 1; index++)
assign ReadLineSetsF[index] = ReadDataLineM[((index+1)*16)+16-1 : (index*16)];
assign ReadLineSetsF[LINELEN/16-1] = {16'b0, ReadDataLineM[LINELEN-1:LINELEN-16]};
assign ReadLineSetsF[index] = ReadDataLine[((index+1)*16)+16-1 : (index*16)];
assign ReadLineSetsF[LINELEN/16-1] = {16'b0, ReadDataLine[LINELEN-1:LINELEN-16]};
assign FinalInstrRawF = ReadLineSetsF[PAdr[$clog2(LINELEN / 32) + 1 : 1]];
if (`XLEN == 64) assign ReadDataWord = {32'b0, FinalInstrRawF};
else assign ReadDataWord = FinalInstrRawF;
@ -192,22 +190,22 @@ module cache #(parameter integer LINELEN,
onehotdecoder #(LOGWPL)
adrdec(.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]),
.decoded(MemPAdrDecodedW));
.decoded(MemPAdrDecoded));
assign SRAMWordEnable = SRAMLineWriteEnableM ? '1 : MemPAdrDecodedW;
assign SRAMWordEnable = SRAMLineWriteEnable ? '1 : MemPAdrDecoded;
assign SRAMLineWayWriteEnableM = SRAMLineWriteEnableM ? VictimWay : '0;
assign SRAMLineWayWriteEnable = SRAMLineWriteEnable ? VictimWay : '0;
mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0),
.d1(SRAMLineWayWriteEnableM),
.s(SRAMLineWriteEnableM),
mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnable ? WayHit : '0),
.d1(SRAMLineWayWriteEnable),
.s(SRAMLineWriteEnable),
.y(SRAMWayWriteEnable));
mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
.d1(CacheMemWriteData),
.s(SRAMLineWriteEnableM),
.s(SRAMLineWriteEnable),
.y(SRAMWriteData));
@ -256,8 +254,8 @@ module cache #(parameter integer LINELEN,
.RW, .Atomic, .CPUBusy, .CacheableM, .IgnoreRequest,
.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdr, .SetValid,
.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM,
.SRAMLineWriteEnableM, .SelEvict, .SelFlush,
.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnable,
.SRAMLineWriteEnable, .SelEvict, .SelFlush,
.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache,
.VDWriteEnable, .LRUWriteEn);

26
pipelined/src/cache/cachefsm.sv vendored
View File

@ -61,8 +61,8 @@ module cachefsm
output logic ClearValid,
output logic SetDirty,
output logic ClearDirty,
output logic SRAMWordWriteEnableM,
output logic SRAMLineWriteEnableM,
output logic SRAMWordWriteEnable,
output logic SRAMLineWriteEnable,
output logic SelEvict,
output logic LRUWriteEn,
output logic SelFlush,
@ -115,8 +115,8 @@ module cachefsm
ClearValid = 1'b0;
SetDirty = 1'b0;
ClearDirty = 1'b0;
SRAMWordWriteEnableM = 1'b0;
SRAMLineWriteEnableM = 1'b0;
SRAMWordWriteEnable = 1'b0;
SRAMLineWriteEnable = 1'b0;
SelEvict = 1'b0;
LRUWriteEn = 1'b0;
SelFlush = 1'b0;
@ -134,7 +134,7 @@ module cachefsm
CacheStall = 1'b0;
SelAdr = 2'b00;
SRAMWordWriteEnableM = 1'b0;
SRAMWordWriteEnable = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0;
@ -168,7 +168,7 @@ module cachefsm
SelAdr = 2'b01;
end
else begin
SRAMWordWriteEnableM = 1'b1;
SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1;
NextState = STATE_READY;
@ -191,7 +191,7 @@ module cachefsm
else if (RW[0] & CacheableM & CacheHit) begin
SelAdr = 2'b01;
CacheStall = 1'b0;
SRAMWordWriteEnableM = 1'b1;
SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1;
@ -235,7 +235,7 @@ module cachefsm
end
STATE_MISS_WRITE_CACHE_LINE: begin
SRAMLineWriteEnableM = 1'b1;
SRAMLineWriteEnable = 1'b1;
CacheStall = 1'b1;
NextState = STATE_MISS_READ_WORD;
SelAdr = 2'b01;
@ -258,7 +258,7 @@ module cachefsm
STATE_MISS_READ_WORD_DELAY: begin
//SelAdr = 2'b01;
SRAMWordWriteEnableM = 1'b0;
SRAMWordWriteEnable = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0;
if(&RW & Atomic[1]) begin // amo write
@ -267,7 +267,7 @@ module cachefsm
NextState = STATE_CPU_BUSY_FINISH_AMO;
end
else begin
SRAMWordWriteEnableM = 1'b1;
SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1;
NextState = STATE_READY;
@ -285,7 +285,7 @@ module cachefsm
end
STATE_MISS_WRITE_WORD: begin
SRAMWordWriteEnableM = 1'b1;
SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
SelAdr = 2'b01;
LRUWriteEn = 1'b1;
@ -323,14 +323,14 @@ module cachefsm
STATE_CPU_BUSY_FINISH_AMO: begin
SelAdr = 2'b01;
SRAMWordWriteEnableM = 1'b0;
SRAMWordWriteEnable = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0;
if(CPUBusy) begin
NextState = STATE_CPU_BUSY_FINISH_AMO;
end
else begin
SRAMWordWriteEnableM = 1'b1;
SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1;
NextState = STATE_READY;