Rose Thompson
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3a0e28fea0
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Added missing spi debugger.
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2024-09-02 14:47:31 -07:00 |
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Rose Thompson
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8d40a0a092
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Changed names of fpga IP modules to match textbook. Updated boot.h to
use the correct clock speed for #DEFINE for UART in the zero stage
bootloader.
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2024-08-22 13:56:50 -07:00 |
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Rose Thompson
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38ddbf860e
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Fixed bug with mmcm not generating the 4th clock.
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2024-05-30 16:19:28 -05:00 |
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Rose Thompson
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9703055758
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The FPGA is synthesizing with the rvvi and ethernet hardware.
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2024-05-30 15:37:17 -05:00 |
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Rose Thompson
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6b7ff50a84
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Reduced Arty A7 clock speed to 20Mhz to support Zicclsm.
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2023-11-13 16:44:02 -06:00 |
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Ross Thompson
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06efd2cdde
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Pushed performance of arty a7 to 23Mhz.
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2023-07-31 14:13:09 -05:00 |
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Ross Thompson
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065e5e98c9
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Improved timing constraints for arty a7 to push clock speed to 20Mhz.
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2023-07-24 10:46:49 -05:00 |
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Ross Thompson
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2752e5de4c
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Fixed a bunch of timing constraints for the arty a7 board.
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2023-07-19 17:08:16 -05:00 |
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Ross Thompson
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30d017c258
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Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster.
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2023-04-17 12:16:31 -05:00 |
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Ross Thompson
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fe692dacce
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Finally got the arty a7 to build.
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2023-04-17 11:54:22 -05:00 |
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Ross Thompson
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4ad33d7acc
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OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(
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2023-04-17 11:10:19 -05:00 |
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Ross Thompson
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5591b447d6
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Fixed more issues with arty a7 constarints.
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2023-04-16 13:25:02 -05:00 |
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Ross Thompson
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2f8359e6cc
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Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.
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2023-04-14 18:02:16 -05:00 |
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