113 Commits

Author	SHA1	Message	Date
David Harris	38ef8eebbb	Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables	2022-07-08 08:44:37 +00:00
David Harris	425fec0f41	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-07 22:00:59 +00:00
Katherine Parry	c581fba4aa	modified wally shared	2022-07-07 21:59:43 +00:00
David Harris	f865994ba1	fixing port errors	2022-07-07 21:57:10 +00:00
Katherine Parry	7771f7b3eb	added load and store test	2022-07-07 21:48:51 +00:00
David Harris	f2915129ab	Preliminary SRAM integration	2022-07-07 19:56:20 +00:00
Ross Thompson	d716c25275	Fixed an issue with direct map cache's nextway logic. ... Also found a small error in the replacement policy.	2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye	d8ea12c6f4	fixed concatenation syntax	2022-07-05 22:36:54 +00:00
Katherine Parry	8f98f3bfab	added rv32 double precision stores - untested	2022-06-28 21:33:31 +00:00
David Harris	8372bc86a7	Removing unused signals	2022-05-12 14:36:15 +00:00
David Harris	cb1a7d54a4	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-05-03 08:53:35 -07:00
David Harris	4fbf78e049	clean up sram1p1rw; still doesn't work on Modelsim 2022.1	2022-05-03 08:31:54 -07:00
David Harris	7e3f75a35d	Formatting cache.sv	2022-05-03 10:53:20 +00:00
David Harris	bc132c3e20	sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera	2022-05-03 03:50:41 -07:00
David Harris	3f2ec0499f	Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense.	2022-05-03 03:45:41 -07:00
Ross Thompson	ab9738d3be	Hacky fix to prevent ITLBMissF and TrapM bug.	2022-04-12 17:56:23 -05:00
Ross Thompson	b2a77da96b	Changed sram1p1rw to have the same type of bytewrite enables as bram.	2022-03-30 11:38:25 -05:00
Ross Thompson	3dbf6790e1	Towards allowing dtim + bus.	2022-03-11 14:58:21 -06:00
Ross Thompson	81a2fbb6d2	mild cleanup.	2022-03-11 13:05:47 -06:00
Ross Thompson	11e5aad38a	Moved subcachelineread inside the cache. There is some ugliness to still resolve.	2022-03-11 12:44:04 -06:00
Ross Thompson	a12016e69b	Moved subcacheline read inside the cache.	2022-03-11 11:03:36 -06:00
Ross Thompson	326ecda060	removed unused parameter.	2022-03-11 10:43:54 -06:00
Ross Thompson	bdfca503fa	Name cleanup.	2022-03-10 18:44:50 -06:00
Ross Thompson	d77adbd673	Signal name cleanup.	2022-03-10 18:26:58 -06:00
Ross Thompson	83133f8c47	Partially working byte write enables. Works for cache, but not dtim or bus only.	2022-03-10 16:11:39 -06:00
Ross Thompson	d5f524a15e	Added byte write enables to cache SRAMs.	2022-03-10 15:48:31 -06:00
Ross Thompson	60e6c1ffa7	Moved cacheable signal into cache.	2022-03-08 16:34:02 -06:00
David Harris	48705457d5	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
Ross Thompson	fcbb577f31	Cache mods to be consistant with diagrams.	2022-02-14 12:40:51 -06:00
Ross Thompson	6e1a0af5d0	Eliminated more ports in cacheway.	2022-02-13 15:53:46 -06:00
Ross Thompson	a440bc2ac5	More cache cleanup.	2022-02-13 15:47:27 -06:00
Ross Thompson	1e7e59bdbd	Changed names of signals in cache.	2022-02-13 15:06:18 -06:00
Ross Thompson	f87a6f2c63	More cache cleanup.	2022-02-13 12:38:39 -06:00
Ross Thompson	f5c4bca47e	Formating improvements to cache.	2022-02-11 23:10:58 -06:00
Ross Thompson	6fa9490d0b	More cache simplifications.	2022-02-11 22:54:05 -06:00
Ross Thompson	ae2011eb07	Reduced seladr to 1 bit as second bit is same as selflush.	2022-02-11 22:41:36 -06:00
Ross Thompson	cb3d71a63d	Reduced complexity of the address selection during flush.	2022-02-11 22:27:27 -06:00
Ross Thompson	a0ee2f3d99	Removed redundant signals from cache.	2022-02-11 22:23:47 -06:00
Ross Thompson	aa04778d0b	Cache fsm simplifications.	2022-02-11 15:16:45 -06:00
Ross Thompson	e6c8cfd49b	Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.	2022-02-11 15:09:00 -06:00
Ross Thompson	83adacbee3	Simplified cache fsm.	2022-02-11 14:54:57 -06:00
Ross Thompson	c8e6884926	Fixed bug. ... It was possible for DTLBMissM to prevent a dcache flush.	2022-02-11 14:00:01 -06:00
David Harris	15fb7fee60	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
Ross Thompson	f23817bf69	Replacement policy cleanup.	2022-02-10 11:42:40 -06:00
Ross Thompson	411997010b	Replacement policy cleanup.	2022-02-10 11:40:10 -06:00
Ross Thompson	3a0af5d9e9	Cleanup + critical path optimizations.	2022-02-10 11:11:16 -06:00
Ross Thompson	fc68c2f09a	Cache name clarifications.	2022-02-10 10:50:17 -06:00
Ross Thompson	e00d404154	More cache cleanup.	2022-02-10 10:43:37 -06:00
Ross Thompson	65803ebe98	structural muxes.	2022-02-09 19:36:21 -06:00
Ross Thompson	2a989e6d05	More cache cleanup.	2022-02-09 19:29:15 -06:00