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Author	SHA1	Message	Date
Rose Thompson	35a3d2e43a	Merge pull request #879 from JacobPease/main ... main	2024-07-12 09:32:13 -05:00
Jacob Pease	7f72fb8583	Updated riscv,isa-extensions property with the correct syntax. Added riscv,cbom-block-size.	2024-07-12 09:28:54 -05:00
Jordan Carlin	a4967138b6	Merge pull request #875 from ross144/main	2024-07-11 18:05:14 -07:00
Rose Thompson	8f52e4ae42	Merge pull request #878 from JacobPease/main ... Commented out riscv,isa-extensions from Arty device tree until Linux kernel is updated.	2024-07-11 11:25:24 -05:00
Jacob Pease	1a2607c3d9	Commented out riscv,isa-extensions from Arty device tree until Linux kernel is updated.	2024-07-11 10:53:18 -05:00
Rose Thompson	f83e6cf771	Fixed issue #874.	2024-07-08 14:48:52 -05:00
Rose Thompson	15b23ceb4d	Merge pull request #866 from davidharrishmc/dev ... First version of iterelf running; removed directory support from wsim	2024-07-07 10:27:22 -05:00
David Harris	9098a55ea3	Fixed lint error in imperas derived config	2024-07-06 05:36:12 -07:00
David Harris	bcbe9eec81	Added lockstep simulations for coverage, wally-riscv-arch-test, buildroot boot to nightly / buildroot regression	2024-07-05 22:13:34 -07:00
David Harris	84c687080d	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-07-05 21:42:26 -07:00
David Harris	9f5e7b8653	Merge pull request #851 from kevindkim723/intdivb ... Reduce Bit widths for IDIV on FPU	2024-07-05 21:42:19 -07:00
David Harris	02a7a1696b	git ignore	2024-07-05 21:35:10 -07:00
David Harris	ffb248dc65	Fixed issue 868 about tlbmisc.S coverage test failing due to HPTW writing wrong address when updateing A bit	2024-07-05 21:32:57 -07:00
David Harris	9279b2d56a	Added imperas configuration for Lee	2024-07-05 09:13:18 -07:00
David Harris	ced8038343	Defined memory to be inaccessible by default	2024-07-05 08:34:28 -07:00
David Harris	604f9d3a45	Fixed imperas.ic prefix for vcs	2024-07-04 12:31:00 -07:00
David Harris	873bd61296	Fixed perl path in derivgen	2024-07-04 12:30:11 -07:00
David Harris	12717a65f2	Fixed location of imperas.ic with new misa_B_Zba_Zbb_Zbs	2024-07-04 12:29:59 -07:00
David Harris	775930ae4f	Fixes to memfile generation for rv32. Updated new misa.B in imperas.ic, but need new version of ImperasDV to test	2024-07-04 07:36:56 -07:00
David Harris	8645441d00	Testbench automatically creates memfile, label, addr files if they are out of date or missing	2024-07-03 16:52:16 -07:00
David Harris	9b120bb3aa	fix timeout in iterelf	2024-07-03 16:34:14 -07:00
David Harris	4528b4ee2a	Fix wsim to use absolute path for ELF	2024-07-03 15:10:02 -07:00
David Harris	f7797d6092	First version of iterelf running; removed directory support from wsim	2024-07-03 14:54:46 -07:00
Rose Thompson	764f46a174	Merge pull request #865 from davidharrishmc/dev ... EBU HPROT based on instruction/data, sim progress	2024-07-03 08:04:43 -07:00
David Harris	af4403342f	renamed run_vcs.py to run_vcs, added instr/data in ebu	2024-07-03 08:02:38 -07:00
David Harris	a2fb6a21c5	Removed testbench-imperas now that wsim supports lockstep and single ELF files	2024-07-03 06:25:32 -07:00
Rose Thompson	dc2b596425	Merge pull request #863 from davidharrishmc/dev ... Regression runs buildroot to login prompt; VCS lockstep progress	2024-07-03 05:58:40 -07:00
David Harris	1b62d2116a	VCS lockstep working	2024-07-02 18:05:13 -07:00
David Harris	aff0ad9c02	Progress on VCS; run_vcs rewritten in Python to ease passing parameters	2024-07-02 14:23:34 -07:00
David Harris	e72c8b8e09	Watchdog timeout on buildroot boot is a halting criteria	2024-07-02 14:22:51 -07:00
David Harris	a0729d074b	regression --nightly --buildroot runs buildroot boot in Verilator all the way to login prompt and checks success	2024-07-02 14:20:40 -07:00
David Harris	38b0c10f9b	Updated wallyTracer to be compatible with VCS	2024-07-02 04:47:53 -07:00
Jordan Carlin	2b4f12916e	Merge pull request #858 from davidharrishmc/dev ... Regression Improvements	2024-07-01 20:04:31 -07:00
Kevin Kim	ec4d4e2a8b	param defs lint	2024-06-30 19:15:42 -07:00
David Harris	68a105d5d8	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-06-29 05:35:46 -07:00
Kevin Kim	b04d387e7c	removed redundant signals	2024-06-28 22:13:35 -07:00
Kevin Kim	6cb6ff429b	Revert "intdivble changes" ... This reverts commit 3618c6c593.	2024-06-28 21:28:09 -07:00
Kevin Kim	3618c6c593	intdivble changes	2024-06-28 21:19:10 -07:00
Jordan Carlin	b0f5fbe497	Merge pull request #861 from stineje/main ... Temporarily removing Q tests as not everyone has tests	2024-06-28 12:54:18 -07:00
James Stine	f660779ba9	Fix for Q causing it to error out - commented out line for ISA and reset-val so can be put back	2024-06-28 12:17:15 -05:00
James Stine	8bb08fefe7	add three programs to APT to make sure they are there for new installs	2024-06-28 12:16:08 -05:00
David Harris	c972a914c8	Removed +plusarg_save because it doesn't silence VCS	2024-06-28 07:48:01 -07:00
David Harris	4a3532bf5a	VCS lockstep progress	2024-06-28 07:19:03 -07:00
David Harris	6cf250821d	Added VCS +plusarg_save to silence compiler	2024-06-28 06:53:44 -07:00
David Harris	e795143983	Turned off debug access to speed up VCS	2024-06-28 06:43:14 -07:00
David Harris	29c94e8abb	Regression fully running with Verilator, which is now the default and much faster than the others	2024-06-28 06:17:40 -07:00
David Harris	31b54fb247	Progress on VCS lockstep	2024-06-27 11:16:17 -07:00
David Harris	d933c80c55	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2024-06-27 07:07:08 -07:00
David Harris	4d87de2600	Merge pull request #855 from jordancarlin/derivgen_fix ... FPU without privilege modes + derived config fixes	2024-06-27 07:06:33 -07:00
Jordan Carlin	e7d4a2ee81	Trim down no priv regression tests	2024-06-27 07:01:55 -07:00