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https://github.com/openhwgroup/cvw
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Merge pull request #863 from davidharrishmc/dev
Regression runs buildroot to login prompt; VCS lockstep progress
This commit is contained in:
Rose Thompson
GitHub
commit
dc2b596425
@ -692,7 +692,7 @@ def main():
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# Define tests that we can run
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if (args.tests == "nightly"):
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test_list = [["python", "regression-wally", "--nightly"]]
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test_list = [["python", "regression-wally", "--nightly --buildroot"]]
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elif (args.tests == "test"):
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test_list = [["python", "regression-wally", ""]]
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elif (args.tests == "test_lint"):
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@ -170,7 +170,7 @@ derivconfigtests = [
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["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf"]],
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["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf", "arch64zfad"]],
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["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64i", "arch64zfaf", "arch64zfad"]],
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["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i", "wally64q", "arch64zfaf", "arch64zfad"]],
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["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i", "arch64zfaf", "arch64zfad"]], # "wally64q" when Q is supported again in riscof config file
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]
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bpredtests = [
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@ -312,7 +312,6 @@ regressionDir = WALLY + '/sim'
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os.chdir(regressionDir)
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coveragesim = "questa" # Questa is required for code/functional coverage
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#defaultsim = "vcs" # Default simulator for all other tests; change to Verilator when flow is ready
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#defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
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defaultsim = "verilator" # Default simulator for all other tests
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@ -320,6 +319,7 @@ coverage = '--coverage' in sys.argv
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fp = '--fp' in sys.argv
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nightly = '--nightly' in sys.argv
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testfloat = '--testfloat' in sys.argv
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buildroot = '--buildroot' in sys.argv
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if (nightly):
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nightMode = "--nightly";
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@ -345,22 +345,27 @@ configs = [
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grepfile = WALLY + "/sim/verilator/logs/all_lints.log")
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]
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# run full buildroot boot simulation (slow) if buildroot flag is set. Start it early to overlap with other tests
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if (buildroot):
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addTests(tests_buildrootboot, defaultsim)
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if (coverage): # only run RV64GC tests on Questa in coverage mode
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addTests(tests64gc_nofp, "questa")
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if (fp):
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addTests(tests64gc_fp, "questa")
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else:
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for sim in sims:
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addTests(tests_buildrootshort, sim)
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if (not (buildroot and sim == defaultsim)): # skip shot buildroot sim if running long one
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addTests(tests_buildrootshort, sim)
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addTests(tests, sim)
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addTests(tests64gc_nofp, sim)
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addTests(tests64gc_fp, sim)
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# run derivative configurations in nightly regression
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# run derivative configurations in nightly regression
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if (nightly):
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# addTests(tests_buildrootboot, defaultsim)
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addTests(derivconfigtests, defaultsim)
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# testfloat tests
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if (testfloat): # for testfloat alone, just run testfloat tests
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configs = []
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8
bin/wsim
8
bin/wsim
@ -41,7 +41,13 @@ def LaunchSim(ElfFile, flags):
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print(f"Running VCS on " + args.config + " " + args.testsuite)
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if (args.gui):
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args.args += "gui"
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cmd = cd + "; ./run_vcs " + args.config + " " + args.testsuite + " " + args.args + " " + flags
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if (args.args == ""):
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vcsargs = ""
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else:
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vcsargs = " --args " + args.args
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if (ElfFile != ""):
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ElfFile = " --elffile " + ElfFile
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cmd = cd + "; ./run_vcs.py " + args.config + " " + args.testsuite + vcsargs + ElfFile + " " + flags
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print(cmd)
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os.system(cmd)
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84
sim/vcs/run_vcs.py
Executable file
84
sim/vcs/run_vcs.py
Executable file
@ -0,0 +1,84 @@
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#!/usr/bin/python3
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# run_vcs
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# David_Harris@hmc.edu 2 July 2024
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# Run VCS on a given file, passing appropriate flags
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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import argparse
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import os
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import subprocess
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# run a Linux command and return the result as a string in a form that VCS can use
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def runfindcmd(cmd):
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# print("Executing: " + str(cmd) )
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res = subprocess.check_output(cmd, shell=True)
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res = str(res)
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res = res.replace("\\n", " ") # replace newline with space
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res = res.replace("\'", "") # strip off quotation marks
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res = res[1:] # strip off leading b from byte string
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return res
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parser = argparse.ArgumentParser()
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parser.add_argument("config", help="Configuration file")
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parser.add_argument("testsuite", help="Test suite (or none, when running a single ELF file) ")
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parser.add_argument("--elffile", "-e", help="ELF file name", default="")
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parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true")
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parser.add_argument("--fcov", "-f", help="Code & Functional Coverage", action="store_true")
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parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
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parser.add_argument("--lockstep", "-l", help="Run ImperasDV lock, step, and compare.", action="store_true")
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# GUI not yet implemented
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#parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
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args = parser.parse_args()
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print("run_vcs Config=" + args.config + " tests=" + args.testsuite + " elffile=" + args.elffile + " lockstep=" + str(args.lockstep) + " args='" + args.args + "'")
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cfgdir = "$WALLY/config"
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srcdir = "$WALLY/src"
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tbdir = "$WALLY/testbench"
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wkdir = "$WALLY/sim/vcs/wkdir/" + args.config + "_" + args.testsuite
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covdir = "$WALLY/sim/vcs/cov/" + args.config + "_" + args.testsuite
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logdir = "$WALLY/sim/vcs/logs"
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os.system("mkdir -p " + wkdir)
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os.system("mkdir -p " + covdir)
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os.system("mkdir -p " + logdir)
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# Find RTL source files
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rtlsrc_cmd = "find " + srcdir + ' -name "*.sv" ! -path "' + srcdir + '/generic/mem/rom1p1r_128x64.sv" ! -path "' + srcdir + '/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "' + srcdir + '/generic/mem/rom1p1r_128x32.sv" ! -path "' + srcdir + '/generic/mem/ram2p1r1wbe_2048x64.sv"'
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rtlsrc_files = runfindcmd(rtlsrc_cmd)
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tbcommon_cmd = 'find ' + tbdir+'/common -name "*.sv" ! -path "' + tbdir+'/common/wallyTracer.sv"'
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tbcommon_files = runfindcmd(tbcommon_cmd)
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RTL_FILES = tbdir+'/testbench.sv ' + str(rtlsrc_files) + ' ' + str(tbcommon_files)
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# Include directories
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INCLUDE_PATH="+incdir+" + cfgdir + "/" + args.config + " +incdir+" + cfgdir + "/deriv/" + args.config + " +incdir+" + cfgdir + "/shared +incdir+$WALLY/tests +incdir+" + tbdir + " +incdir+" + srcdir
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# lockstep mode
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if (args.lockstep):
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LOCKSTEP_OPTIONS = " +define+USE_IMPERAS_DV +incdir+$IMPERAS_HOME/ImpPublic/include/host +incdir+$IMPERAS_HOME/ImpProprietary/include/host $IMPERAS_HOME/ImpPublic/source/host/rvvi/*.sv $IMPERAS_HOME/ImpProprietary/source/host/idv/*.sv " + tbdir + "/common/wallyTracer.sv"
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LOCKSTEP_SIMV = "-sv_lib $IMPERAS_HOME/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model"
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else:
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LOCKSTEP_OPTIONS = ""
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LOCKSTEP_SIMV = ""
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# coverage mode
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if (args.coverage):
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COV_OPTIONS = "-cm line+cond+branch+fsm+tgl -cm_log " + wkdir + "/coverage.log -cm_dir " + wkdir + "/coverage"
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else:
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COV_OPTIONS = ""
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# Simulation commands
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OUTPUT="sim_out"
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VCS_CMD="vcs +lint=all,noGCWM,noUI,noSVA-UA,noIDTS,noNS,noULCO,noCAWM-L,noWMIA-L,noSV-PIU,noSTASKW_CO,noSTASKW_CO1,noSTASKW_RMCOF -suppress +warn -sverilog +vc -Mupdate -line -full64 -lca -ntb_opts sensitive_dyn " + INCLUDE_PATH # Disabled Debug flags; add them back for a GUI mode -debug_access+all+reverse -kdb +vcs+vcdpluson
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VCS = VCS_CMD + " -Mdir=" + wkdir + " " + srcdir + "/cvw.sv " + LOCKSTEP_OPTIONS + " " + COV_OPTIONS + " " + RTL_FILES + " -o " + wkdir + "/" + OUTPUT + " -work " + wkdir + " -Mlib " + wkdir + " -l " + logdir + "/" + args.config + "_" + args.testsuite + ".log"
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SIMV_CMD= wkdir + "/" + OUTPUT + " +TEST=" + args.testsuite + " " + args.elffile + " " + args.args + " -no_save " + LOCKSTEP_SIMV
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# Run simulation
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print("Executing: " + str(VCS) )
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subprocess.run(VCS, shell=True)
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subprocess.run(SIMV_CMD, shell=True)
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if (args.coverage):
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COV_RUN = "urg -dir " + wkdir + "/coverage.vdb -format text -report IndividualCovReport/" + args.config + "_" + args.testsuite
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subprocess.run(COV_RUN, shell=True)
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@ -56,8 +56,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
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logic [`NUM_REGS-1:0] frf_wb;
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logic [4:0] frf_a4;
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logic frf_we4;
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logic [P.XLEN-1:0] CSRArray [logic[11:0]];
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logic [P.XLEN-1:0] CSRArrayOld [logic[11:0]];
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logic [P.XLEN-1:0] CSRArray [4095:0];
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logic [P.XLEN-1:0] CSRArrayOld [4095:0];
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logic [`NUM_CSRS-1:0] CSR_W;
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logic CSRWriteM, CSRWriteW;
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logic [11:0] CSRAdrM, CSRAdrW;
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@ -26,7 +26,8 @@
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module watchdog #(parameter XLEN, WatchDogTimerThreshold)
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(input clk,
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input reset
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input reset,
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string TEST
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);
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// check for hang up.
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@ -46,9 +47,14 @@ module watchdog #(parameter XLEN, WatchDogTimerThreshold)
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always_comb begin
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WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
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if(WatchDogTimeOut) begin
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$display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
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$stop;
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end
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if (TEST == "buildroot") $display("Watch Dog Time Out triggered. This is a normal termination for a full buildroot boot. Check sim/<simulator>/logs/buildroot_uart.log to check if the boot printed the login prompt.");
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else $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
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`ifdef QUESTA
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$stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
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`else
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$finish;
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`endif
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end
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end
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endmodule
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@ -118,10 +118,9 @@ module testbench;
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TEST = "none";
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if (!$value$plusargs("ElfFile=%s", ElfFile))
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ElfFile = "none";
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else begin
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end
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if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT))
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INSTR_LIMIT = 0;
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//$display("TEST = %s ElfFile = %s", TEST, ElfFile);
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// pick tests based on modes supported
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//tests = '{};
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@ -613,7 +612,7 @@ module testbench;
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// watch for problems such as lockup, reading unitialized memory, bad configs
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watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset); // check if PCW is stuck
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watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset, .TEST); // check if PCW is stuck
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ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM,
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dut.core.ifu.PCM, InstrM, dut.core.lsu.IEUAdrM, InstrMName);
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riscvassertions #(P) riscvassertions(); // check assertions for a legal configuration
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