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Author SHA1 Message Date
David Harris
348e74b8be Updated wrapper generation to be automatic without specifying WRAPPER=1; instead looks for cvw_t in the file. Also starting to add OSU 130 nm synthesis. 2023-10-19 10:44:03 -07:00
David Harris
7c1606264a Adjusted synthesis scripts to report on DESIGN even when a wrapper is used 2023-10-19 06:16:52 -07:00
David Harris
4873b9c0a8 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-10-18 14:40:19 -07:00
David Harris
4469484f4a Merge pull request #435 from kipmacsaigoren/synth_wrapper_gen 
synth wrapper generation bug fix
 2023-10-18 14:34:37 -07:00
Kevin Kim
7b35da5245 wrapper bug fix 2023-10-18 14:29:46 -07:00
David Harris
48d42c1e7c Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates 2023-10-18 05:50:41 -07:00
David Harris
b76c371e45 Config file cleanup 2023-10-18 05:38:36 -07:00
David Harris
c685837d08 Merge pull request #433 from ross144/main 
Reverted linux testbench to not check for match against QEMU.
 2023-10-17 11:13:11 -07:00
Rose Thompson
010fbf7319 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-17 10:01:35 -05:00
Rose Thompson
faea7db1b2 Reverted linux testbench to not check for match against QEMU. 2023-10-17 10:00:50 -05:00
Rose Thompson
6ae5934cd2 Merge pull request #431 from davidharrishmc/dev 
Dev
 2023-10-16 17:36:31 -05:00
David Harris
fab9fbd7f1 Merged testbench 2023-10-16 13:52:24 -07:00
David Harris
1a6e57f8c0 Renamed wally-config to config in many comments 2023-10-16 13:49:09 -07:00
David Harris
ac4216b43d Incorporated new AMO tests from riscv-arch-test 2023-10-16 10:25:45 -07:00
David Harris
6245748ed7 Added CSR permission tests for mconfigptr, menvcfg, mseccfg, etc. 2023-10-15 15:31:03 -07:00
David Harris
b4891d88db Added WALLY minfo test for rv32 2023-10-15 06:48:22 -07:00
David Harris
434d6b2c5c minfo test working again with mconfigptr for RV64 2023-10-15 06:41:52 -07:00
David Harris
4cab203900 Merge pull request #429 from ross144/main 
renamed imperas testbench to testbench-imperas.sv, fixed SDC timing bug
 2023-10-13 15:32:43 -07:00
Rose Thompson
8f2ca2ae15 Added missing files. 2023-10-13 15:10:58 -05:00
Rose Thompson
8d4cdcbd1a Renamed testbench_imperas.sv to testbench-imperas.sv 2023-10-13 14:56:45 -05:00
Rose Thompson
c1d6fddea8 Removed P.FPGA from testbench. 2023-10-13 14:08:17 -05:00
Ross Thompson
c43377afff Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-13 13:44:19 -05:00
Ross Thompson
7ab2dc1447 Merge branch 'main' of github.com:ross144/cvw 2023-10-13 12:30:52 -05:00
Ross Thompson
4634756e20 Change to flash-sd.sh to fix relative path to device tree. 2023-10-13 12:30:21 -05:00
Ross Thompson
1a060d7efa Fixed bug with flash script. 2023-10-10 18:05:35 -05:00
Ross Thompson
d33c966a42 Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock. 2023-10-10 17:46:12 -05:00
David Harris
519d7ce664 Merge pull request #424 from ross144/main 
Fixed issue #412 The root cause was DTLB miss leads to page fault exception with concurrent I$ miss.  The HPTW hits all entries in the D$ and quickly faults.  However the I$ is still waiting on the main memory. The trap then interrupts the atomimicity of the bus fetch and breaks the next several instructions.
 2023-10-10 07:09:15 -07:00
Ross Thompson
5e65138552 Merge branch 'main' of github.com:ross144/cvw 2023-10-09 16:08:07 -05:00
Ross Thompson
e02d3577ec Fixed issue #412 
The root cause was DTLB miss leads to page fault exception with concurrent I$ miss.  The HPTW hits all entries in the D$ and quickly faults.  However the I$ is still waiting on the main memory.
The trap then interrupts the atomimicity of the bus fetch and breaks the next several instructions.

The simplest solution is to use CommittedF to delay Exceptions like with Interrupts.  Note this cannot happen with CommittedM.  If the ITLB misses and the D$ also need to fetch a from the bus an ITLB page fault exception will not trigger the trap until a few stages later.
 2023-10-09 16:03:37 -05:00
Rose Thompson
c9006f6d33 Merge pull request #422 from eroom1966/main 
Update to IDV
 2023-10-06 07:51:14 -05:00
eroom1966
d690708194 add in new .sv file 2023-10-06 13:47:05 +01:00
Lee Moore
0a0d6dd25e Merge branch 'openhwgroup:main' into main 2023-10-06 11:46:45 +01:00
David Harris
9ee4fde7aa Merge pull request #421 from ross144/main 
Oups. When fixing the linux-imperasdv testbench I accidentally introduced a bug to the tracer.
 2023-10-05 11:31:50 -07:00
Ross Thompson
0ca7bf6593 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-05 13:00:59 -05:00
Ross Thompson
fc83f33615 Oups. When fixing the linux-imperasdv testbench I accidentally introduced a bug to the tracer. 2023-10-05 13:00:46 -05:00
David Harris
59f9345db9 Merge pull request #420 from ross144/main 
Fixed Imperas Linux testbench
 2023-10-05 09:34:04 -07:00
Ross Thompson
824f37bba4 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-05 10:39:06 -05:00
Ross Thompson
81c44a4cb3 Fixed imperas linux testbench. 2023-10-04 17:11:47 -05:00
Rose Thompson
b66e5b42ce Merge pull request #419 from davidharrishmc/dev 
Zcb extension
 2023-10-04 15:39:38 -05:00
David Harris
28752303be Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there 2023-10-04 12:28:12 -07:00
David Harris
19a6bbb01b UpdateDA cleanup: don't assert UpdateDA when there is no SVADU 2023-10-04 09:57:13 -07:00
Rose Thompson
825f80d6a5 Merge pull request #418 from davidharrishmc/dev 
Added MENVCFG.HADE bit and updated SVADU to depend on this bit
 2023-10-04 11:56:44 -05:00
David Harris
d526d28804 Added MENVCFG.HADE bit and updated SVADU to depend on this bit 2023-10-04 09:34:28 -07:00
David Harris
928dbcd56d Merge pull request #415 from ross144/main 
added new branch predictor post processing script and updated buildroot config script to support c++
 2023-10-03 20:25:56 -07:00
Ross Thompson
d23eda1305 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-10-03 17:43:29 -05:00
Ross Thompson
3156d5abab Somehow the arty A7 was missing the update for the console baud rate setting. 2023-10-03 17:37:13 -05:00
Rose Thompson
e35d9e721e Merge pull request #417 from VictorClements/main 
Update Top Level Makefile
 2023-10-03 09:36:48 -05:00
Rose Thompson
fd4155f67d Merge pull request #416 from stineje/main 
Update to Wally for test float fixes and other ancillary quality improvements
 2023-10-03 09:36:17 -05:00
VictorClements
999a50d9ee Update Makefile 
"make riscof" and "make testfloat" were run in backward order, leading to some of the make issues when a user is setting up for the very first time.
 2023-10-03 07:32:45 -07:00
James E. Stine
8b9ddd731c Update TeX docs divsqrt examples by removing ancillary files (apologies for previously pushing) 2023-10-03 09:25:26 -05:00