Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-03 10:15:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #429 from ross144/main

Browse Source 
renamed imperas testbench to testbench-imperas.sv, fixed SDC timing bug
This commit is contained in:
David Harris 2023-10-13 15:32:43 -07:00 committed by GitHub
commit 4cab203900
7 changed files with 22 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
fpga/src/axi_sdc_controller.v
View File

@ -205,7 +205,7 @@ always @(posedge clock)
reset_sync <= {reset_sync[1:0], !async_resetn};
reg [7:0] clock_cnt;
reg clock_state;
(* mark_debug = "true" *) reg clock_state;
(* mark_debug = "true" *) reg clock_posedge;
reg clock_data_in;
wire fifo_almost_full;
@ -265,7 +265,7 @@ wire sd_dat_oe;
// IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t));
// IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t));
always @(negedge clock) begin
always @(negedge sdio_clk) begin
// Output data delayed by 1/2 clock cycle (5ns) to ensure
// required hold time: default speed - min 5ns, high speed - min 2ns (actual 5ns)
if (sdio_reset) begin

2
linux/sdcard/flash-sd.sh
View File

@ -56,7 +56,7 @@ done
IMAGES=$BUILDROOT/output/images
FW_JUMP=$IMAGES/fw_jump.bin
LINUX_KERNEL=$IMAGES/Image
DEVICE_TREE=$IMAGES/$DEVICE_TREE
#DEVICE_TREE=$IMAGES/$DEVICE_TREE
SDCARD=${ARGS[0]}

2
sim/wally-imperas.do
View File

@ -40,7 +40,7 @@ vlog +incdir+../config/$1 \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2bin.sv \
../src/cvw.sv \
../testbench/testbench_imperas.sv \
../testbench/testbench-imperas.sv \
../testbench/common/*.sv \
../src/*/*.sv \
../src/*/*/*.sv \

0
testbench/testbench_imperas.sv → testbench/testbench-imperas.sv
View File

2
testbench/testbench-linux.sv
View File

@ -27,7 +27,7 @@
`include "config.vh"
import cvw::*;
`define DEBUG_TRACE 0
`define DEBUG_TRACE 1
// Debug Levels
// 0: don't check against QEMU
// 1: print disagreements with QEMU, but only halt on PCW disagreements

16
testbench/testbench-xcelium.sv
View File

@ -265,9 +265,7 @@ module testbench;
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
// the addr of each label and fill the array. To expand, add more elements to this array
// and initialize them to zero (also initilaize them to zero at the start of the next test)
if(!P.FPGA) begin
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
end
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
end
////////////////////////////////////////////////////////////////////////////////
@ -361,21 +359,21 @@ module testbench;
////////////////////////////////////////////////////////////////////////////////
// load memories with program image
////////////////////////////////////////////////////////////////////////////////
if (P.FPGA) `define TB_FPGA // this is a gross hack for xcelium and verilator
if (P.SDC_SUPPORTED) `define TB_SDC_SUPPORTED // this is a gross hack for xcelium and verilator
if (P.IROM_SUPPORTED) `define TB_IROM_SUPPORTED
if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED
if (P.BUS_SUPPORTED) `define TB_BUS_SUPPORTED
always @(posedge clk) begin
if (LoadMem) begin
if (P.FPGA) begin
`ifdef TB_FPGA
if (P.SDC_SUPPORTED) begin
`ifdef TB_SDC_SUPPORTED
string romfilename, sdcfilename;
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
//$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
//$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
// shorten sdc timers for simulation
dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
//dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
`endif
end
else if (P.IROM_SUPPORTED) begin

22
testbench/testbench.sv
View File

@ -37,9 +37,9 @@ module testbench;
parameter DEBUG=0;
parameter TEST="none";
parameter PrintHPMCounters=1;
parameter BPRED_LOGGER=0;
parameter I_CACHE_ADDR_LOGGER=0;
parameter D_CACHE_ADDR_LOGGER=0;
parameter BPRED_LOGGER=1;
parameter I_CACHE_ADDR_LOGGER=1;
parameter D_CACHE_ADDR_LOGGER=1;
`include "parameter-defs.vh"
@ -260,9 +260,7 @@ module testbench;
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
// the addr of each label and fill the array. To expand, add more elements to this array
// and initialize them to zero (also initilaize them to zero at the start of the next test)
if(!P.FPGA) begin
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
end
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
end
////////////////////////////////////////////////////////////////////////////////
@ -344,14 +342,14 @@ module testbench;
////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (LoadMem) begin
if (P.FPGA) begin
if (P.SDC_SUPPORTED) begin
string romfilename, sdcfilename;
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
//$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
//$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
// shorten sdc timers for simulation
dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
//dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
end
else if (P.IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
@ -377,7 +375,7 @@ module testbench;
assign {HRESPEXT, HRDATAEXT} = '0;
end
if(P.FPGA) begin : sdcard
if(P.SDC_SUPPORTED) begin : sdcard
// *** fix later
/* -----\/----- EXCLUDED -----\/-----
sdModel sdcard
@ -394,7 +392,7 @@ module testbench;
assign SDCIntr = '0;
end
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCIntr);