95 Commits

Author	SHA1	Message	Date
Ross Thompson	326ecda060	removed unused parameter.	2022-03-11 10:43:54 -06:00
Ross Thompson	bdfca503fa	Name cleanup.	2022-03-10 18:44:50 -06:00
Ross Thompson	d77adbd673	Signal name cleanup.	2022-03-10 18:26:58 -06:00
Ross Thompson	50789f9ddd	Byte write enables are passing all configs now.	2022-03-10 17:26:32 -06:00
Ross Thompson	d5f524a15e	Added byte write enables to cache SRAMs.	2022-03-10 15:48:31 -06:00
David Harris	b1340653cf	bit write update	2022-03-09 19:09:20 +00:00
David Harris	004853c312	Refactored SRAM bit write enable	2022-03-09 17:49:28 +00:00
Ross Thompson	acd60218b8	Removed unused signal.	2022-03-08 16:58:26 -06:00
Ross Thompson	cc21414051	Added parameter to spillsupport.	2022-03-08 16:38:48 -06:00
Ross Thompson	60e6c1ffa7	Moved cacheable signal into cache.	2022-03-08 16:34:02 -06:00
Ross Thompson	97d64201f7	Fixed bug with DAPageFault being wrong when HPTW writes not supported.	2022-02-23 10:54:34 -06:00
Ross Thompson	53f13d4cbc	More spillsupport more structual.	2022-02-23 10:27:14 -06:00
Ross Thompson	c23f6c7d90	Fixed bug with spill support and Instruction DA Page Faults.	2022-02-23 10:16:12 -06:00
Ross Thompson	62e1a97287	Added generates to pcnextf muxes for privileged and caches.	2022-02-22 22:45:00 -06:00
Ross Thompson	6a52f95cc8	Minor busdp cleanup.	2022-02-22 17:28:26 -06:00
Ross Thompson	ca59778c5a	Annotated IFU for mux changes.	2022-02-21 17:20:34 -06:00
Ross Thompson	62f5f1e622	Broken state. address translation not working after changes to hptw to support atomic updates to PT.	2022-02-16 23:37:36 -06:00
Ross Thompson	c9e33208e3	Moved a few muxes around after sww changes.	2022-02-16 15:43:03 -06:00
Ross Thompson	71ed49bf2b	cleanup of signal names.	2022-02-16 15:29:08 -06:00
David Harris	caa4d83e57	t push ... Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-02-14 01:22:22 +00:00
Ross Thompson	1e7e59bdbd	Changed names of signals in cache.	2022-02-13 15:06:18 -06:00
David Harris	f5678e25db	Synthesis cleanup	2022-02-12 06:25:12 +00:00
Ross Thompson	20456097cd	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-02-11 10:47:21 -06:00
Ross Thompson	2f2a4f4500	Fixed subtle and infrequenct bug. ... Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.	2022-02-11 10:46:06 -06:00
David Harris	15fb7fee60	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
Ross Thompson	fc6dc52618	Fixed bugs in ifu spills and missing reset on bus data register.	2022-02-10 18:11:57 -06:00
Ross Thompson	382d5fab0f	Cleanup.	2022-02-10 11:27:15 -06:00
Ross Thompson	3a0af5d9e9	Cleanup + critical path optimizations.	2022-02-10 11:11:16 -06:00
Ross Thompson	911ee36b22	Removed all possilbe paths to PreSelAdr from TrapM.	2022-02-09 19:20:10 -06:00
Ross Thompson	e0a605e95d	Cleanup IFU.	2022-02-08 14:54:53 -06:00
Ross Thompson	cecbb3362d	rv32e works for now. Still need to optimize.	2022-02-08 14:21:55 -06:00
Ross Thompson	39149c618f	Moved some muxes back into the bp.	2022-02-08 14:17:44 -06:00
Ross Thompson	d5d9bb9d4d	Temporary commit which gets the no branch predictor implementation working.	2022-02-08 14:13:55 -06:00
Ross Thompson	3cd067ac6a	Finished merge.	2022-02-08 11:36:24 -06:00
David Harris	0feb624bab	Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration	2022-02-06 01:22:40 +00:00
Ross Thompson	1766c0f5ba	Removed unused ports from caches and buses.	2022-02-04 22:52:51 -06:00
Ross Thompson	dce4f8a0e5	Cleanup.	2022-02-04 22:40:51 -06:00
Ross Thompson	53551ab533	Moved the hwdata mux back into the busdp.	2022-02-04 22:39:13 -06:00
Ross Thompson	34cf77797a	Merged together the two sub cache line read muxes. ... One mux was used for loads and the other for eviction.	2022-02-04 22:30:04 -06:00
David Harris	23868a33bc	Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.	2022-02-05 04:16:18 +00:00
Ross Thompson	c846368537	Moved the sub cache line read logic to lsu/ifu.	2022-02-04 20:42:53 -06:00
David Harris	bdf1a8ba73	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
Ross Thompson	910d16b642	More cleanup of IFU.	2022-02-01 14:32:27 -06:00
Ross Thompson	dce9ee12b4	IFU and LSU now share the same busdp module.	2022-01-31 16:25:41 -06:00
Ross Thompson	a04aa283cb	partial ifu cleanup.	2022-01-31 16:08:53 -06:00
Ross Thompson	b05abc1795	cleanup.	2022-01-31 13:29:04 -06:00
Ross Thompson	ef770fd183	Encapsulated the bus data path into a separate module.	2022-01-31 10:15:48 -06:00
Ross Thompson	d52c5b0393	LSU and IFU cleanup.	2022-01-28 15:26:06 -06:00
Ross Thompson	de0bef4f5b	Updated wave.do to match the ifu/lsu changes.	2022-01-28 14:37:15 -06:00
Ross Thompson	147d71fd46	Clean up of mmu instances in IFU and LSU.	2022-01-28 14:02:05 -06:00