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2a7467c76d
cvw/fpga/constraints
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Ross Thompson 2a7467c76d Separated timing constraints from ILA.
2021-12-01 18:15:04 -06:00
..
constraints.xdc Got fpga synthesis running from scripts. 2021-12-01 16:59:04 -06:00
debug.xdc Separated timing constraints from ILA. 2021-12-01 18:15:04 -06:00