Github_Repos/cvw
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335 Commits

Author SHA1 Message Date
David Harris
30b085911a bpred tab cleanup 2023-01-24 05:42:34 -08:00
Ross Thompson
07308e2c14 Removed mark_debug from all source code. 2023-01-20 18:47:36 -06:00
Ross Thompson
b8a699270e More cleanup and formatting. 2023-01-20 12:34:40 -06:00
Ross Thompson
f1049be6c1 More cleanup and formatting. 2023-01-20 12:09:21 -06:00
Ross Thompson
4a2d02ab28 Formatting. 2023-01-20 11:51:10 -06:00
Ross Thompson
78e8598ec8 Added comment about needed changes in BTB. 2023-01-19 17:28:00 -06:00
Ross Thompson
75391f4b56 Formatting. 2023-01-19 15:06:37 -06:00
Ross Thompson
40d62ec0d1 Formatting. 2023-01-19 14:18:46 -06:00
Ross Thompson
999477bb02 Formatting and name changes. 2023-01-19 14:16:29 -06:00
Ross Thompson
0bbf6e4ae2 Formatting. 2023-01-18 19:26:20 -06:00
Ross Thompson
21b2b10e78 Formatting spillsupport. 2023-01-18 19:25:54 -06:00
Ross Thompson
db48e547f0 Formatting. 2023-01-18 19:11:30 -06:00
Ross Thompson
9170827c98 Reduced complexity of spill logic by ensuring the irom outputs offset instrutions on a spill. 2023-01-18 19:10:34 -06:00
Ross Thompson
e79c403fe1 More IROM cleanup. 2023-01-18 18:47:02 -06:00
Ross Thompson
63577cbf4a Cleanup dtim and irom. 2023-01-18 18:44:30 -06:00
Ross Thompson
2d945963e6 Added comments to decompress.sv. May want to consider additional documentation. 2023-01-18 18:26:51 -06:00
Ross Thompson
c5c4a3c011 Formatting 2023-01-18 16:58:03 -06:00
Ross Thompson
c3096eea2a Cleaned up ahbcacheinterface. 2023-01-17 22:13:56 -06:00
Ross Thompson
4720b28272 Formatting progress. 2023-01-17 22:10:31 -06:00
Ross Thompson
4e1e10a729 Fixed bug with gshare repair from branch class miss prediction. 2023-01-15 14:39:48 -06:00
Ross Thompson
77756e12eb Possible improvement to gshare. 2023-01-13 18:50:01 -06:00
Ross Thompson
4a73018d6e Merge branch 'rastemp' 2023-01-13 18:09:50 -06:00
Ross Thompson
17aebb8a3b Partial fix to RAS prediction accurracy. 2023-01-13 18:05:47 -06:00
Ross Thompson
53c8042276 Signal renames for ras. 2023-01-13 15:56:10 -06:00
Ross Thompson
8e3e8591a6 Removed 1 bit from instruction classification. 2023-01-13 15:19:53 -06:00
Ross Thompson
37481fce77 More branch predictor cleanup. 
Found small bug. The decode stage was using the predicted instruction class rather than the decoded instruction class.
 2023-01-13 12:57:18 -06:00
Ross Thompson
f7dacb59f9 Possible minor enhancement to gshare. 2023-01-13 12:32:39 -06:00
Ross Thompson
b5250466ec Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2023-01-11 23:02:14 -06:00
sarah-harris
3b363f5f9d privilege unit -> privileged unit in ifu.sv 
privilege unit -> privileged unit in ifu.sv
 2023-01-11 16:33:08 -08:00
David Harris
7d93659f6b changed name to CORE-V-WALLY 2023-01-11 15:15:08 -08:00
David Harris
8f4b33c900 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2023-01-11 15:13:58 -08:00
Ross Thompson
5f31c681ff Updated branch predictor. 2023-01-11 17:00:45 -06:00
David Harris
b911056e66 Changed Wally to CORE-V Wally 2023-01-11 14:03:44 -08:00
Ross Thompson
aa5300389f Optimized gshare. 2023-01-10 18:12:48 -06:00
David Harris
e92cffbb5e Changed MIT license to Solderpad License 2023-01-10 11:35:20 -08:00
Ross Thompson
0a77d80224 Added folded gshare predictor with k=16 and depth=10. 2023-01-09 14:41:03 -06:00
Ross Thompson
f032eae7f5 Might have actually solved the gshare bug. 2023-01-09 00:11:25 -06:00
Ross Thompson
97feea2f48 Possibly working speculative global history. 2023-01-08 23:46:53 -06:00
Ross Thompson
a35fb3addd core part of global history works now. forwarding is still broken. 2023-01-08 23:35:02 -06:00
David Harris
15b829bbf7 Removed unused signals 2023-01-07 06:06:54 -08:00
David Harris
9bdf79bfe6 Removed unused signals; added check for atomic in pmachecker 2023-01-07 05:59:56 -08:00
David Harris
d1839b6db2 Remove conditional from inside decompress module 2023-01-07 05:51:47 -08:00
David Harris
0a011f4548 Remove unused signals 2023-01-07 05:46:22 -08:00
Ross Thompson
34f8f2c47a Added more missing files. 2023-01-06 00:12:08 -06:00
Ross Thompson
0081ff92f9 Addd missing file. 2023-01-06 00:09:18 -06:00
Ross Thompson
e34f80db2f More branch predictor cleanup. 2023-01-05 17:19:27 -06:00
Ross Thompson
010168a69e Keep around the old gshare. 2023-01-05 15:55:46 -06:00
Ross Thompson
f3d871f2c3 Added speculative gshare. 2023-01-05 14:18:00 -06:00
Ross Thompson
3637067ace Officially added global history with speculation to types of branch predictors. 2023-01-05 14:04:09 -06:00
Ross Thompson
8ca6c1255e More branch predictor cleanup. 2023-01-05 13:36:51 -06:00
Ross Thompson
bca87d326b Two bit predictor cleanup. 2023-01-05 13:27:22 -06:00
Ross Thompson
87c9682311 Simplified gshare. 2023-01-04 23:51:09 -06:00
Ross Thompson
f8c656f1e0 Simiplified global history branch predictor. 2023-01-04 23:41:55 -06:00
davidharrishmc
f1c950a5a7 Update decompress.sv 
typo
 2023-01-04 17:01:26 -08:00
Ross Thompson
5d844801d2 Fixed problems with changes to ram2p. 2022-12-29 17:13:48 -06:00
Ross Thompson
1f42098758 Added about moving decompressed config generate. 2022-12-27 15:04:55 -06:00
Ross Thompson
1d11ff6153 Added missing assignment for no branch predictor mode. 2022-12-24 17:08:29 -06:00
Ross Thompson
b5a85b55f1 Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 
Generate WFIStallM in the privileged unit rather than generate in hazard.
Cleaned up the hazard cause logic to be consistent across all causes.
 2022-12-23 15:10:37 -06:00
Ross Thompson
6b105bd217 Renamed IFU and LSU stalls. 2022-12-22 21:56:33 -06:00
Ross Thompson
ce7e1073fa Success we've replaced TrapM with FlushD in the IFU. 2022-12-22 21:36:49 -06:00
Ross Thompson
677f6f8737 Partial cleanup for BP. 2022-12-22 20:33:38 -06:00
Ross Thompson
942acb354e Closing in on icache flushed by FlushD rather than TrapM. 2022-12-22 20:19:09 -06:00
Ross Thompson
47d61984ad First pass at resolving ifu flush on trap rather than FlushD. 2022-12-22 15:53:06 -06:00
Ross Thompson
0cb2cf9a5b Changed GatedStallF to GatedStallD. 2022-12-21 16:12:55 -06:00
Ross Thompson
2b1e9f8bed The optimzied PC+2/4 logic still hanges on wally32priv. 2022-12-21 09:19:34 -06:00
Ross Thompson
a2329c8e9d Renamed PCPlusUpperF to PCPlus4F. 2022-12-21 09:18:30 -06:00
Ross Thompson
3fc121ef70 Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0. 
Switched to even simplier PC+2/4 logic.
 2022-12-21 09:00:09 -06:00
Ross Thompson
bc5d5e902a Comments about PC+2/4. 2022-12-21 08:35:43 -06:00
Ross Thompson
6152c028db Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 18:09:37 -06:00
Ross Thompson
cba2ed64e5 Moved privileged pc logic into privileged unit. 2022-12-20 17:55:45 -06:00
David Harris
07dc11a508 IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI 2022-12-20 15:38:30 -08:00
Ross Thompson
b4bdf446cc Implement FENCE.I as NOP when ZIFENCEI is not supported. 2022-12-20 17:34:11 -06:00
David Harris
f03d4e6b5a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-12-20 14:43:33 -08:00
David Harris
9133b3a7a4 FPU remove unused signals 2022-12-20 14:43:30 -08:00
Ross Thompson
637df763ca Renumbered bits for PCPlusUpper. 2022-12-20 16:33:49 -06:00
Ross Thompson
ca6076445b Merge branch 'main' of github.com:davidharrishmc/riscv-wally 2022-12-20 12:58:59 -06:00
Ross Thompson
d35fc5e2a6 Reorganized IFU PCNextF logic. 2022-12-20 12:58:54 -06:00
David Harris
c26c3b76ea Renamed renamed sram to ram 2022-12-20 08:36:45 -08:00
David Harris
b575f6242e Renamed SRAM2P1R1W to lower case 2022-12-20 02:09:36 -08:00
Ross Thompson
67e0b021ae several options for pcnextf on fence.i 2022-12-19 23:33:12 -06:00
Ross Thompson
d18ef45c18 More bp/ifu pcmux cleanup. 2022-12-19 23:16:58 -06:00
Ross Thompson
761cf54dcc Moved more muxes inside bp. 2022-12-19 22:51:55 -06:00
Ross Thompson
0097c166d6 Begin cleanup of ifu. partial move of pc muxes inside bp. 2022-12-19 22:46:11 -06:00
David Harris
2393915bf2 Simplified InstrRawD register 2022-12-19 15:18:42 -08:00
Ross Thompson
c253b882be Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage. 2022-12-15 09:53:35 -06:00
Ross Thompson
dbc3dac03d Removed unused flushf. 2022-12-11 16:28:11 -06:00
Ross Thompson
ad7dd56180 Renamed CPUBusy to GatedStallF in IFU. 2022-12-11 15:54:19 -06:00
Ross Thompson
6d573b32d2 Changed CPUBusy to Stall in ebu modules. 2022-12-11 15:51:35 -06:00
Ross Thompson
232f866ad1 Renamed CPUBusy to Stall in cache. 2022-12-11 15:49:34 -06:00
Ross Thompson
f09b9e1572 Finished merge of kip and ross's ifu fix. 2022-12-09 16:52:22 -06:00
Ross Thompson
981ac3963a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-12-09 16:42:16 -06:00
Kip Macsai-Goren
055ca9ee37 Addded fix for 32 bit periph test and added test to regression 2022-12-06 09:56:08 -08:00
Ross Thompson
5dbcf8fb10 Fixed bug Kip found. 
The no cache and no bus versions lacked assignment of CacheCommittedF in the IFU.
 2022-12-06 10:37:45 -06:00
Ross Thompson
faa13a96e0 I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps. 2022-11-16 15:38:37 -06:00
Ross Thompson
b53f8eceef Renamed Flush to FlushStage in the cache. 2022-11-14 14:11:05 -06:00
Ross Thompson
13e6f7d80b Changed names of cache signals. 2022-11-13 21:36:12 -06:00
Ross Thompson
54544ae251 Moved all remaining bus logic from the LSU into ahbcacheinterface. 2022-11-11 14:30:32 -06:00
Ross Thompson
8658a25218 Renamed Word to Beat for ahbcacheinterface. 2022-11-09 17:52:50 -06:00
Ross Thompson
be8e0eee1b Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). 
FlushW prevents writting the cache, dtim, and bus state.  FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
 2022-11-07 15:50:55 -06:00
Ross Thompson
44171c342d Reduced complexity of logic supressing cache operations. 2022-11-01 15:23:24 -05:00