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Author SHA1 Message Date
Ross Thompson
63fb70fa61 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-03 23:49:28 -06:00
Ross Thompson
105763d938 Fixed icache stalling cpu when doing an uncached operation. 2022-01-03 23:49:19 -06:00
Kip Macsai-Goren
a763c37959 update 64 bit tests to make make work correctly and general cleanup 2022-01-04 05:02:33 +00:00
Kip Macsai-Goren
03e26f29a4 Update 32 bit memory tests to make make work correcttly and generally cleanup 2022-01-04 04:59:47 +00:00
Kip Macsai-Goren
e13c050fa1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-04 04:55:36 +00:00
Ross Thompson
2d1cb0c3a3 Reordered inputs/outputs in caches. 2022-01-03 22:52:50 -06:00
Ross Thompson
ff24718c28 Added generate around the spill logic so it is only used if supporting compressed instructions. 2022-01-03 22:23:04 -06:00
Ross Thompson
120a9d6a58 Minor improvement to icache. 2022-01-03 22:00:35 -06:00
Ross Thompson
89f4b920ff More Icache clean up. 2022-01-03 21:22:34 -06:00
Ross Thompson
2f7cb82c72 Major icache cleanup. 2022-01-03 21:12:17 -06:00
Ross Thompson
b045d84147 Removed spill support from icache. 2022-01-03 21:03:02 -06:00
Ross Thompson
8c7638688b The ifu now directly supports compressed without the icache providing the implemenation. 
The icache still constains all the orignal muxing logic to handle spills.  This should be removed.
 2022-01-03 20:49:47 -06:00
Ross Thompson
324362eee5 Almost working compressed instructions with compressed detection and processing in ifu rather than icache. 2022-01-03 18:10:15 -06:00
Ross Thompson
82fbc502e0 Prepared the ifu and icache for moving spills to ifu. 2022-01-03 17:09:36 -06:00
Ross Thompson
d77ddd2cbf Fixed bug with the icache. 2022-01-03 15:55:19 -06:00
Ross Thompson
c501276067 Fixed a bug where the instruction fetch got out of sync with the icache. 2022-01-03 13:27:15 -06:00
David Harris
95407a6ea7 Replaced && and || with & and | in non-fp files per new style guidelines 2022-01-02 21:47:21 +00:00
David Harris
77c00e996b Started adding asynchronous TIMECLK for CLINT 2022-01-02 21:18:16 +00:00
Katherine Parry
cf7aa4e8ae some errors in FP ArchTests fixed 2022-01-01 23:50:23 +00:00
David Harris
25dd532b6a Removed .* from MMU. 2021-12-31 07:19:51 +00:00
David Harris
272e884581 Removed .* from CSRs 2021-12-31 07:11:03 +00:00
David Harris
ae3767bd54 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-31 06:40:25 +00:00
David Harris
62e6aed7e5 Simplified performance counters 2021-12-31 06:40:21 +00:00
Ross Thompson
2096d45c23 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-30 18:10:36 -06:00
Ross Thompson
7055bfa4a7 Added mux to select between uncache instruction requests and cached instructions requests. 
Cacheless design almost works with the exception of compressed instructions.
 2021-12-30 18:09:37 -06:00
Ross Thompson
9432d9b72b Fixed wave.do. 2021-12-30 17:57:07 -06:00
Ross Thompson
89dc598a83 Patched up the linux-wave.do file. 2021-12-30 17:53:43 -06:00
David Harris
19a47bd276 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-30 23:40:02 +00:00
David Harris
4066ea6463 Fixes to counters; buildroot still broken 2021-12-30 23:39:59 +00:00
Ross Thompson
2a2db23803 Working without dcache. 2021-12-30 16:01:31 -06:00
Ross Thompson
6942f20180 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-30 15:52:15 -06:00
Ross Thompson
89303579ee Progress on non dcache mode working. 2021-12-30 15:51:07 -06:00
David Harris
adbcf835f8 Moved SDC folder into uncore 2021-12-30 21:38:24 +00:00
Ross Thompson
54d71006b1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-30 15:26:41 -06:00
Ross Thompson
fd77022f73 No dcache now supported. Does not pass regression tests however. 2021-12-30 15:26:32 -06:00
David Harris
ffc2a2097a Removed unnecessary generate inside hptw 2021-12-30 21:21:00 +00:00
David Harris
25c634da8b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-30 21:15:00 +00:00
David Harris
700c3f8ca6 Removed carry-save multiplier option from muldiv 2021-12-30 21:14:57 +00:00
Ross Thompson
bd531d1996 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-30 14:56:24 -06:00
Ross Thompson
59a38e3efd Separated the icache from the bus fetching logic. I was able to share the same fsm between the lsu and ifu. 2021-12-30 14:56:17 -06:00
David Harris
451f37729f Added names to generate blocks 2021-12-30 20:55:48 +00:00
Ross Thompson
9ea308b2d7 icache separated from bus fetch fsm. Does not work yet. 2021-12-30 14:23:05 -06:00
Kip Macsai-Goren
63b1bddc31 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-30 17:32:03 +00:00
David Harris
91b8d7d2eb erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-30 17:22:22 +00:00
David Harris
e084c8868f Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion 2021-12-30 17:22:18 +00:00
Ross Thompson
f3fe91eba1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-30 11:01:22 -06:00
Ross Thompson
3803b9cd2d Changed names of Icache signals. 2021-12-30 11:01:11 -06:00
David Harris
c1969ca142 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-30 16:49:36 +00:00
David Harris
da402f93cc Fixed page table entreis so WALLY-MMU-SV32, SV39, SV48 now run 2021-12-30 16:46:19 +00:00
Ross Thompson
26ad3fc11f Icache now works with any sized cache line a power of 2, greater than or equal to 32. 2021-12-30 10:37:57 -06:00