Ross Thompson
301d54fea8
Significant refactoring of testbench.
2023-06-14 17:02:49 -05:00
Ross Thompson
4d2bb0ea83
Removed old configs from function name module.
2023-06-14 16:35:55 -05:00
Ross Thompson
8f09e17dc7
Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x.
2023-06-14 14:11:25 -05:00
Ross Thompson
6330e8084c
more testbench improvements.
2023-06-14 12:23:26 -05:00
Ross Thompson
6e42b9f865
Continued improvements to testbench.
2023-06-14 12:11:55 -05:00
Ross Thompson
10c6c08136
Resolved the duplicated check signature issue.
2023-06-14 11:50:12 -05:00
Ross Thompson
3a78d4ca73
Fixed another issue with the timing of memory resets in the new testbench.
2023-06-13 16:24:38 -05:00
Ross Thompson
af8ca85a5b
Now have most of the regression tests running again.
2023-06-13 15:09:40 -05:00
Ross Thompson
836bc4a4f7
Cleaned up testbench more.
2023-06-13 14:05:17 -05:00
Ross Thompson
4bdecf8c6d
Compacted memory resets.
2023-06-13 13:57:58 -05:00
Ross Thompson
91a22c3a8a
More cleanup.
2023-06-13 13:54:07 -05:00
Ross Thompson
9869b26556
Fixed the multliple reads of the same preload memory file.
2023-06-13 13:52:02 -05:00
Ross Thompson
df62f3964c
The testbench now at least runs the arch64i in rv64gc config. Still has several issues
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1. need to remove all dead code
2. seems to still be double reading memory files sometimes.
3. batch mode does not work.
2023-06-13 13:18:46 -05:00
Ross Thompson
fe72264de3
The new testbench is almost working except the shadow copy is not working.
2023-06-12 15:08:23 -05:00
Ross Thompson
9eeac21113
Progress towards new testbench.
2023-06-12 14:06:17 -05:00
Ross Thompson
3ef2031791
Created temporary wrapper for lint.
2023-06-12 11:49:51 -05:00
Ross Thompson
ee4352975c
This parameterizes the testbench but does not use the verilator updates or the new testbench.
2023-06-12 11:00:30 -05:00
Ross Thompson
39c8f11191
Fixed the garbled output in embench transcript.
2023-06-08 10:43:46 -05:00
Ross Thompson
4ddbbd6948
Merge pull request #314 from davidharrishmc/dev
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Make and FP script improvements
2023-06-06 12:38:26 -04:00
Ross Thompson
918464c236
Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem.
2023-06-05 15:42:05 -05:00
David Harris
65dd99af0c
Support all testfloat tests with parameterized design
2023-05-31 06:30:21 -07:00
Ross Thompson
8648d0c25c
Hacked it together, but I think testfloat is working.
2023-05-30 15:51:13 -05:00
Ross Thompson
04d0fd94f0
Merge branch 'param-lim-merge'
2023-05-26 16:25:35 -05:00
Ross Thompson
88cc473c68
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-05-24 13:00:50 -05:00
Ross Thompson
930fb67308
Trying to figure out why the parameterization slowed down modelsim so much.
2023-05-24 12:44:42 -05:00
Ross Thompson
2ddb8c7c78
Merge pull request #297 from davidharrishmc/dev
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Verilator testbench changes
2023-05-22 13:29:54 -04:00
David Harris
163b05f1ce
Removed force from branch predictor initialization
2023-05-22 09:57:41 -07:00
David Harris
84dac82def
Initial testbench cleanup for Verilator
2023-05-22 09:51:46 -07:00
Ross Thompson
664231c0da
Merge branch 'localhistory'
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Repair to wave file.
Created implementations of local history. Part of my Ph.D. research.
2023-05-22 10:13:31 -05:00
David Harris
7b0d1a7883
Factored FMA tests out of the main 32/64 f/d tests to run in parallel and speed up sim
2023-05-16 11:37:01 -07:00
Ross Thompson
3a98fb8680
Baseline localhistory with speculative repair built.
2023-05-05 15:23:45 -05:00
Ross Thompson
8b0791b6b5
I think ahead pipelining is working for local history.
2023-05-03 12:52:32 -05:00
Ross Thompson
0904a9b97f
Swapped the m and k parameters for local history predictor.
2023-05-02 10:52:41 -05:00
Kevin Wan
9ca738547e
fixed tests.vh test lines
2023-04-28 07:47:59 -07:00
Kevin Wan
39c9cd5ee9
added tests for pmppriority module
2023-04-27 16:12:43 -07:00
Noah Limpert
4ec31de316
complete camline coverage on IFU and LSU
2023-04-27 14:26:10 -07:00
Noah Limpert
a0e71c26cb
Add in a test that makes match 3 = 0 for all tlb lines
2023-04-20 14:50:06 -07:00
Noah Limpert
7ca44de126
Commiting changes to add coverage to ASID, Global, Megapage size checks.
2023-04-20 14:38:13 -07:00
David Harris
6e612a1693
Update tests.vh
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Missing comma from merge
2023-04-19 06:23:05 -07:00
David Harris
4cbffd7972
Merge branch 'main' into coverage4
2023-04-19 06:16:07 -07:00
David Harris
b63dff098a
Merge branch 'main' into main
2023-04-19 04:50:12 -07:00
David Harris
156a098884
Merge branch 'main' into main
2023-04-19 04:46:51 -07:00
Alec Vercruysse
b3a3af8ed3
add D$ test case to trigger a FlushStage while SetDirtyWay=1
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This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd803bfa44
Cover CacheWay edge case: CacheDataMem we=1 while ce=0.
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This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
2023-04-19 01:34:01 -07:00
Liam
9b72d6ac37
Update tests.vh
2023-04-18 23:15:47 -07:00
Kevin Wan
771124e265
Completely covers all PMPCFG_ARRAY_REGW cases
2023-04-18 21:50:48 -07:00
Kevin Wan
1bdae2285d
PMPCFG_ARRAY_REGW cases
2023-04-18 18:43:50 -07:00
Kevin Thomas
db0ca8695a
Add PR#252 test file to coverage
2023-04-18 17:57:56 -05:00
Limnanthes Serafini
2d9de7b58f
Merge branch 'openhwgroup:main' into code_quality
2023-04-13 19:59:58 -07:00
Limnanthes Serafini
ff72cbc1b2
Finished up testbench reformatting
2023-04-13 19:18:26 -07:00