77 Commits

Author	SHA1	Message	Date
Ross Thompson	7f1ae039b0	Optimization. Able to remove hptw address muxes from the E stage.	2022-09-08 15:51:18 -05:00
David Harris	bc0c7d0cd8	Cleaned up SelBusWord	2022-08-25 11:18:13 -07:00
David Harris	3ba961d1a8	renamed BusBuffer to FetchBuffer	2022-08-25 10:44:39 -07:00
Ross Thompson	ebe4339953	Updated fpga test bench. ... Solved read delay cache bug. Introduced during cache optimizations.	2022-08-21 15:59:54 -05:00
Ross Thompson	2ba390adf4	Possible reduction of ignorerequest.	2022-08-19 18:07:44 -05:00
Ross Thompson	517c0f6c35	Changed signal names.	2022-08-17 16:12:04 -05:00
Ross Thompson	f6e5746e59	Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.	2022-08-17 16:09:20 -05:00
Ross Thompson	413a9bf58b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-01 22:09:11 -05:00
Ross Thompson	57fcf0ef79	Fixed fstore2 in cache?	2022-08-01 22:04:44 -05:00
Ross Thompson	3cd8404917	Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.	2022-08-01 21:08:14 -05:00
Katherine Parry	1bd6351e1f	re-added FStore2 in Cache	2022-07-29 22:54:49 +00:00
Ross Thompson	40e7cda84a	Don't use this commit yet. Untested.	2022-07-24 15:40:52 -05:00
Ross Thompson	05484c4c05	signal name cleanup.	2022-07-22 23:36:27 -05:00
Ross Thompson	27e32980ad	cache cleanup after removing replay on cpubusy.	2022-07-22 23:30:25 -05:00
Ross Thompson	abc79c6c8e	Possible improvement to cache which removes the cpu_busy states.	2022-07-22 23:20:37 -05:00
Ross Thompson	a79e5e11f6	Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.	2022-07-18 23:37:18 -05:00
Katherine Parry	62205ebb3b	renamed FLoad2 to FStore2	2022-07-09 00:26:45 +00:00
Katherine Parry	97e7e619d9	moved fpu ieu write data mux to lsu	2022-07-08 23:56:57 +00:00
Ross Thompson	d716c25275	Fixed an issue with direct map cache's nextway logic. ... Also found a small error in the replacement policy.	2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye	d8ea12c6f4	fixed concatenation syntax	2022-07-05 22:36:54 +00:00
Katherine Parry	8f98f3bfab	added rv32 double precision stores - untested	2022-06-28 21:33:31 +00:00
David Harris	7e3f75a35d	Formatting cache.sv	2022-05-03 10:53:20 +00:00
Ross Thompson	ab9738d3be	Hacky fix to prevent ITLBMissF and TrapM bug.	2022-04-12 17:56:23 -05:00
Ross Thompson	3dbf6790e1	Towards allowing dtim + bus.	2022-03-11 14:58:21 -06:00
Ross Thompson	81a2fbb6d2	mild cleanup.	2022-03-11 13:05:47 -06:00
Ross Thompson	11e5aad38a	Moved subcachelineread inside the cache. There is some ugliness to still resolve.	2022-03-11 12:44:04 -06:00
Ross Thompson	a12016e69b	Moved subcacheline read inside the cache.	2022-03-11 11:03:36 -06:00
Ross Thompson	326ecda060	removed unused parameter.	2022-03-11 10:43:54 -06:00
Ross Thompson	bdfca503fa	Name cleanup.	2022-03-10 18:44:50 -06:00
Ross Thompson	d77adbd673	Signal name cleanup.	2022-03-10 18:26:58 -06:00
Ross Thompson	d5f524a15e	Added byte write enables to cache SRAMs.	2022-03-10 15:48:31 -06:00
Ross Thompson	60e6c1ffa7	Moved cacheable signal into cache.	2022-03-08 16:34:02 -06:00
David Harris	48705457d5	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
Ross Thompson	fcbb577f31	Cache mods to be consistant with diagrams.	2022-02-14 12:40:51 -06:00
Ross Thompson	6e1a0af5d0	Eliminated more ports in cacheway.	2022-02-13 15:53:46 -06:00
Ross Thompson	a440bc2ac5	More cache cleanup.	2022-02-13 15:47:27 -06:00
Ross Thompson	1e7e59bdbd	Changed names of signals in cache.	2022-02-13 15:06:18 -06:00
Ross Thompson	f87a6f2c63	More cache cleanup.	2022-02-13 12:38:39 -06:00
Ross Thompson	f5c4bca47e	Formating improvements to cache.	2022-02-11 23:10:58 -06:00
Ross Thompson	ae2011eb07	Reduced seladr to 1 bit as second bit is same as selflush.	2022-02-11 22:41:36 -06:00
Ross Thompson	cb3d71a63d	Reduced complexity of the address selection during flush.	2022-02-11 22:27:27 -06:00
Ross Thompson	a0ee2f3d99	Removed redundant signals from cache.	2022-02-11 22:23:47 -06:00
Ross Thompson	411997010b	Replacement policy cleanup.	2022-02-10 11:40:10 -06:00
Ross Thompson	3a0af5d9e9	Cleanup + critical path optimizations.	2022-02-10 11:11:16 -06:00
Ross Thompson	fc68c2f09a	Cache name clarifications.	2022-02-10 10:50:17 -06:00
Ross Thompson	e00d404154	More cache cleanup.	2022-02-10 10:43:37 -06:00
Ross Thompson	2a989e6d05	More cache cleanup.	2022-02-09 19:29:15 -06:00
Ross Thompson	911ee36b22	Removed all possilbe paths to PreSelAdr from TrapM.	2022-02-09 19:20:10 -06:00
Ross Thompson	498388c636	Cache cleanup write enables.	2022-02-08 17:52:09 -06:00
Ross Thompson	492c1473f3	Preparing to make a major change to the cache's write enables.	2022-02-08 09:47:01 -06:00