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8,920 Commits 5 Branches 2 Tags 53 MiB
2c487935e6
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47 Commits

Author SHA1 Message Date
David Harris
2c487935e6 Attempt at functional coverage; breaks code and functional coverage 2024-07-15 14:20:48 -07:00
David Harris
04cd2c8ea4 Renamed --coverage to --ccov and moved UCDB files to questa/ucdb 2024-07-15 05:32:16 -07:00
David Harris
12717a65f2 Fixed location of imperas.ic with new misa_B_Zba_Zbb_Zbs 2024-07-04 12:29:59 -07:00
David Harris
775930ae4f Fixes to memfile generation for rv32. Updated new misa.B in imperas.ic, but need new version of ImperasDV to test 2024-07-04 07:36:56 -07:00
Ross Thompson
2d8973df1d Updated wavefile to use new names. 2024-06-19 13:57:28 -07:00
Ross Thompson
64712d2243 Updated wave to match changes in testbench. 2024-06-19 13:51:50 -07:00
Rose Thompson
a88d5f403b Functional coverage works with wally.do 2024-05-28 14:02:54 -05:00
Rose Thompson
0c5b70c40a It's a bit hacky. But I've got functional coverage working with our wally.do script and testbench.sv. 2024-05-28 13:54:48 -05:00
Rose Thompson
48fd365b9d Still don't understand why wally.do can't load testbench.sv with functional coverage. But wally-imperas-cov.do can load testbench.sv with functional coverage. 2024-05-28 13:00:17 -05:00
Rose Thompson
4a1e856b18 Almost working functional coverage in wally.do 
riscvISACOV is now loading, but for some reason I still cannot get it to record anything.
Instead it is just logging the instructions.
 2024-05-27 18:15:12 -05:00
Rose Thompson
92ee56c1a1 Yay. Finally found the bug which prevented wally.do from having functional coverage using riscvISACOV. 
testbench.sv was missing the trace2cov instance.
 2024-05-27 17:25:20 -05:00
Rose Thompson
4c0261fd2c Closer. Needed to reorder includes and defines. 2024-05-27 15:37:16 -05:00
Rose Thompson
ff611016c7 Closer? 2024-05-27 14:11:02 -05:00
Rose Thompson
2985cfb7eb Preliminary work to merge functional coverage into wally.do. 2024-05-27 11:59:13 -05:00
Rose Thompson
a885240fbd temporary commit to help debug merging testbench.sv with testbench-imperas.sv 2024-05-17 12:36:00 -05:00
Rose Thompson
bd8450734b Fixed more bugs with wally.do. 2024-05-17 10:39:00 -05:00
Rose Thompson
46e6459965 Updated script to run linux with imperasDV. 2024-05-14 13:46:27 -05:00
Rose Thompson
970af9551c Fixed bug with gui mode testbench_fp 
removed old wally-linux-imperas.do
 2024-05-14 13:41:20 -05:00
Rose Thompson
30bea18dec Maybe have imperasDV linux simulation merged into wally.do 2024-05-14 12:38:19 -05:00
Rose Thompson
e8f5545076 Got imperasDV running linux simulation again. 
Now need to merge do files.
 2024-05-13 16:43:13 -05:00
Rose Thompson
ceb31fec68 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-05-10 08:54:23 -05:00
Rose Thompson
b027fa44ef Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-05-10 08:53:00 -05:00
Rose Thompson
93ea5b0c1e Fixed wavefile to have function logger. 2024-05-10 08:50:42 -05:00
David Harris
04457d49f7 Updated sim-testfloat-verilator to use wsim 2024-05-10 05:03:24 -07:00
David Harris
37fc45cd35 Updated Questa wally.do to terminate on a compile error 2024-05-06 11:28:00 -07:00
David Harris
1274ec55af Resolved merge conflict 2024-04-26 16:15:23 -07:00
Quswar Abid
f999ccadf4 /cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch 2024-04-26 15:55:39 -07:00
David Harris
5d97858806 Moved functional coverage files to sim/questa and to tests/riscvdv 2024-04-24 11:46:38 -07:00
Quswar Abid
7b441d2881 Bringup of RISCV-DV to collect functional coverage - Update to track RV64IMAFDC_Zicsr related coverpoints from riscvISACOV 2024-04-23 18:20:29 -07:00
slmnemo
554f818a8c Fixed wave.do to match new conditional generate block names 2024-04-16 14:43:38 -07:00
Rose Thompson
1eb1beed95 Fixed merge conflict bug in the last pull request. 2024-04-16 10:32:24 -05:00
slmnemo
4b80457f3e Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory 2024-04-12 21:58:20 -07:00
Rose Thompson
bb072fba84 Fixed the buildroot issue. 2024-04-06 18:25:53 -05:00
Rose Thompson
d0d1166e3f Got the separation of the -G and +variable arguments in the questa do file. 
regression still runs.
 2024-04-06 18:04:48 -05:00
Rose Thompson
cdcff9d368 Updated sim-wally to work with new run scripts. 2024-04-06 16:32:07 -05:00
Rose Thompson
46fdfde7ec Removed unnecessary display from testbench. 2024-04-06 16:10:18 -05:00
David Harris
c73a48cf22 Removed unused wave-dos 2024-04-06 13:52:13 -07:00
David Harris
6b844a2e6e Added GUI support and removed unused wave files 2024-04-06 13:43:06 -07:00
David Harris
3c855e3e90 Passing arguments to buildroot, not yet checking result correctly 2024-04-06 11:42:41 -07:00
David Harris
ac9a21873d Pass TEST to testbench with +TEST=<name> rather than -G TEST=<name> so that we don't have to recompile for every new test 2024-04-06 10:34:21 -07:00
David Harris
347df26713 Fixed regression running; buildroot pending 2024-04-06 09:46:56 -07:00
David Harris
9ee7544d3c TestFloat running; normal testbench broken 2024-04-06 09:28:07 -07:00
David Harris
4b19f6d542 testfloat running through wsim; moved lint, regression, wsim to bin directory so we don't need ./ 2024-04-06 08:22:39 -07:00
David Harris
4cc9dd7583 regression-wally refactoring to support mulitple simulators 2024-04-05 21:45:56 -07:00
David Harris
7b56809323 wsim runs a Questa sim 2024-04-05 19:08:14 -07:00
David Harris
a1d3e5b15e Moved do files into questa 2024-04-05 18:42:48 -07:00
David Harris
a8a03d6011 Reorganizing sim directory for multiple simulators 2024-04-05 18:19:46 -07:00