David Harris
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2b0f8e9cf6
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Started pagetablewalker cleanup: combined state flops shared for both RV versions
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2021-07-17 02:53:52 -04:00 |
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David Harris
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fe8910437a
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Replaced separate PageTypeF and PageTypeM with common PageType
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2021-07-17 02:31:23 -04:00 |
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David Harris
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622a14cbdd
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Removed more unused signals from ahblite
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2021-07-17 02:21:54 -04:00 |
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David Harris
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52fcc47cdf
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Removed rest of HRDATAW from ahblite
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2021-07-17 02:15:24 -04:00 |
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David Harris
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1d171d7ea6
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Commented out HRDATAW logic in ebu
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2021-07-17 02:10:57 -04:00 |
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David Harris
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d6f859da18
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renamed or_rows.sv
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2021-07-16 20:17:03 -04:00 |
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Ross Thompson
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e9649eb1f5
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Made furture progress in the mmu tests.
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2021-07-16 15:56:06 -05:00 |
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Ross Thompson
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abce241f68
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Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
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2021-07-16 14:21:09 -05:00 |
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Ross Thompson
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d3715acf2d
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Fixed walker fault interaction with dcache.
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2021-07-16 12:22:13 -05:00 |
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Ross Thompson
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5ca7dc619c
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Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues.
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2021-07-16 11:12:57 -05:00 |
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Kip Macsai-Goren
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ba5bb12e26
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Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction.
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2021-07-15 18:30:29 -04:00 |
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Ross Thompson
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96aa106852
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Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault.
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2021-07-15 11:56:35 -05:00 |
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Ross Thompson
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4549a9f1c9
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Merge branch 'main' into dcache
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2021-07-15 11:55:20 -05:00 |
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Ross Thompson
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c39a228266
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Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits.
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2021-07-15 11:00:42 -05:00 |
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Ross Thompson
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c954fb510b
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Renamed DCacheStall to LSUStall in hart and hazard.
Added missing logic in lsu.
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2021-07-15 10:16:16 -05:00 |
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Ross Thompson
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f234875779
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dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed.
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2021-07-14 23:08:07 -05:00 |
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Ross Thompson
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6163629204
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Finally have the ptw correctly walking through the dcache to update the itlb.
Still not working fully.
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2021-07-14 22:26:07 -05:00 |
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Katherine Parry
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701ea38964
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Fixed lint warning
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2021-07-14 21:24:48 -04:00 |
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Ross Thompson
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d41c9d5ad9
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Added d cache StallW checks for any time the cache wants to go to STATE_READY.
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2021-07-14 17:25:50 -05:00 |
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Ross Thompson
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d3a1a2c90a
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Fixed d cache not honoring StallW for uncache writes and reads.
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2021-07-14 17:23:28 -05:00 |
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Katherine Parry
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f8b76082e4
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fpu unpacking unit created
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2021-07-14 17:56:49 -04:00 |
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Ross Thompson
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771c7ff130
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Routed CommittedM and PendingInterruptM through the lsu arb.
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2021-07-14 16:18:09 -05:00 |
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Ross Thompson
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1d7aa27316
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Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled.
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2021-07-14 15:47:38 -05:00 |
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Ross Thompson
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3092e5acdf
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Forgot to include one hot decoder.
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2021-07-14 15:46:52 -05:00 |
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Ross Thompson
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e17de4eb11
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Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
This solves the committedM issue.
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2021-07-14 15:00:33 -05:00 |
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James Stine
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a2c0753edb
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put back for now to test fdiv
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2021-07-14 06:48:29 -05:00 |
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Ross Thompson
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ef598d0e79
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Implemented uncached reads.
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2021-07-13 23:03:09 -05:00 |
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Ross Thompson
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b6e5670bc3
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Added CommitedM to data cache output.
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2021-07-13 22:43:42 -05:00 |
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Ross Thompson
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278bbfbe3c
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Partially working changes to support uncached memory access. Not sure what CommitedM is.
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2021-07-13 17:24:59 -05:00 |
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James E. Stine
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45a6e96673
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mod 2 of fpdivsqrt update
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2021-07-13 16:59:17 -04:00 |
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James E. Stine
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d695be3ad0
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Update fpdivsqrt item until move into uarch
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2021-07-13 16:53:20 -04:00 |
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Ross Thompson
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b780e471b4
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Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled.
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2021-07-13 14:51:42 -05:00 |
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Ross Thompson
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51249a0e04
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Fixed the fetch buffer accidental overwrite on eviction.
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2021-07-13 14:21:29 -05:00 |
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Ross Thompson
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2034a6584f
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Dcache AHB address generation was wrong. Needed to zero the offset.
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2021-07-13 14:19:04 -05:00 |
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Ross Thompson
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ee09fa5f58
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Moved StoreStall into the hazard unit instead of in the d cache.
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2021-07-13 13:20:50 -05:00 |
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David Harris
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516b710db6
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Fixed busybear by restoring InstrValidW needed by testbench
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2021-07-13 14:17:36 -04:00 |
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Ross Thompson
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2004b2e044
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Fixed back to back store issue.
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
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2021-07-13 12:46:20 -05:00 |
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David Harris
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9af5cef65a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-07-13 13:26:51 -04:00 |
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David Harris
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283c2cda0e
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added or.sv
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2021-07-13 13:26:40 -04:00 |
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Katherine Parry
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b9edbb15eb
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Fixed writting MStatus FS bits
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2021-07-13 13:22:04 -04:00 |
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Katherine Parry
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acdd2e4504
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Fixed writting MStatus FS bits
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2021-07-13 13:20:30 -04:00 |
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David Harris
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68d1f87101
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Fixed InstrValid from W to M stage for CSR performance counters
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2021-07-13 13:19:13 -04:00 |
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Ross Thompson
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40922cf064
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Fixed subword write. subword read should not feed into subword write.
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2021-07-13 11:21:44 -05:00 |
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David Harris
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4be1e8617f
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Replaced .or with or_rows structural code in MMU read circuitry for synthesis.
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2021-07-13 09:32:02 -04:00 |
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Ross Thompson
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9fe6190763
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Team work on solving the dcache data inconsistency problem.
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2021-07-12 23:46:32 -05:00 |
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Ross Thompson
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8ca8b9075d
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Progress towards the test bench flush.
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2021-07-12 14:22:13 -05:00 |
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Katherine Parry
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a4bd128978
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fcvt.sv cleanup
|
2021-07-11 21:30:01 -04:00 |
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Katherine Parry
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0cc07fda1b
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Almost all convert instructions pass Imperas tests
|
2021-07-11 18:06:33 -04:00 |
|
Ross Thompson
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282bde7205
|
Fixed the spurious AHB requests to address 0. Somehow by not having a default
(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
|
2021-07-10 22:34:47 -05:00 |
|
Ross Thompson
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d9fa3af94d
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Loads are working.
There is a bug when the icache stalls 1 cycle before the d cache.
|
2021-07-10 22:15:44 -05:00 |
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