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Author SHA1 Message Date
David Harris
6e612a1693 Update tests.vh 
Missing comma from merge
 2023-04-19 06:23:05 -07:00
David Harris
3d9ae82dec Merge pull request #259 from AlecVercruysse/coverage4 
D$ Coverage
 2023-04-19 06:17:01 -07:00
David Harris
4cbffd7972 Merge branch 'main' into coverage4 2023-04-19 06:16:07 -07:00
David Harris
6081fcbb45 Merge pull request #258 from liamchalk00/main 
Add test cases for pmpcfg.S
 2023-04-19 04:52:59 -07:00
David Harris
b63dff098a Merge branch 'main' into main 2023-04-19 04:50:12 -07:00
David Harris
7d3bc6171c Merge pull request #257 from koooo142857/main 
PMPCFG_ARRAY_REGW cases
 2023-04-19 04:47:12 -07:00
David Harris
156a098884 Merge branch 'main' into main 2023-04-19 04:46:51 -07:00
David Harris
acde82b23e Merge pull request #255 from kjprime/main 
Add PR#252 test file to coverage
 2023-04-19 04:43:25 -07:00
Alec Vercruysse
faaf266558 CacheFSM logic simplification for AMO operations 
Ran this by Ross.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
de93bd6937 D$ scope-specific coverage exclusions (I$ logic that never fires) 
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.

Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.

There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
b3a3af8ed3 add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd803bfa44 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
9ef85c547b fix unhit exclusion in fdivsqrtfsm 2023-04-19 01:34:01 -07:00
Liam
9b72d6ac37 Update tests.vh 2023-04-18 23:15:47 -07:00
Liam
d74768ce04 Add test cases for pmpcfg.S 2023-04-18 23:06:52 -07:00
Kevin Wan
b5a3ff2d2d a 2023-04-18 22:09:50 -07:00
Kevin Wan
c91784bd5a Merge branch 'main' of https://github.com/koooo142857/cvw into main 2023-04-18 21:55:06 -07:00
koooo142857
c9018b8204 Merge branch 'openhwgroup:main' into main 2023-04-18 21:53:46 -07:00
Kevin Wan
771124e265 Completely covers all PMPCFG_ARRAY_REGW cases 2023-04-18 21:50:48 -07:00
Kevin Wan
1bdae2285d PMPCFG_ARRAY_REGW cases 2023-04-18 18:43:50 -07:00
Cedar Turek
49356aa4ca created fdivsqrtcycles, moved cycles calculation from FSM to preproc 2023-04-18 16:14:45 -07:00
Kevin Thomas
db0ca8695a Add PR#252 test file to coverage 2023-04-18 17:57:56 -05:00
Ross Thompson
224bf74530 Found the first issue. the axi clock converter was stuck in reset because the polarity was reversed. 2023-04-18 17:45:41 -05:00
Cedar Turek
b1dd1a627f gave integer bits to D instead of adding manually everywhere 2023-04-18 15:41:04 -07:00
Cedar Turek
914baf6bb1 moved D flop to preproc 2023-04-18 15:14:17 -07:00
Ross Thompson
367bd0f8dc More debug stuff. 2023-04-18 16:00:10 -05:00
Ross Thompson
668e69fdc9 Added more signals to debugger in hopes I can figure out why the mig is not responding. 2023-04-18 15:51:52 -05:00
Ross Thompson
3588c53e66 It's almost working. 2023-04-18 14:24:59 -05:00
David Harris
4c3aba9722 Merge pull request #252 from mcook26/main 
Increase of TLB coverage in IFU
 2023-04-18 05:49:18 -07:00
Miles Cook
5e45fef838 Increase of TLB coverage in IFU 2023-04-17 18:35:03 -07:00
Ross Thompson
deb0bfc24d Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V. 2023-04-17 20:05:59 -05:00
Ross Thompson
777bec2e24 Fixed timing constraint issue. 2023-04-17 19:53:43 -05:00
Ross Thompson
b2b30936be Found the DDR3 memory is not ready when issuing the first store. 2023-04-17 19:33:13 -05:00
Ross Thompson
fbbba0e5c2 Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8. 2023-04-17 18:39:25 -05:00
Ross Thompson
2cbaa5c27b Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way. 2023-04-17 16:37:18 -05:00
Sydeny
40853f4dc7 increasing lsu coverage by excluding the pmachecher/adrdecs/clintdec or uncoreram signal SizeValid becauseany size is valid so signal is always 1 2023-04-17 14:19:48 -07:00
Ross Thompson
480562e53e Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there. 2023-04-17 16:00:02 -05:00
Sydeny
ee5deb10a7 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-17 13:51:16 -07:00
Ross Thompson
b0f0fb1da7 Adding in the ILA to the arty a7. 2023-04-17 14:54:10 -05:00
David Harris
a413b5c6ca Merge pull request #251 from masonadams25/main 
Removed redundent expression to increase coverage
 2023-04-17 12:37:27 -07:00
Ross Thompson
aa2e874d70 Merge pull request #249 from davidharrishmc/dev 
DV Test Plan, fdivsqrt, merged exclusions
 2023-04-17 14:32:37 -05:00
Mason Adams
56575cb45e Removed redundent expression to increase coverage 2023-04-17 14:13:26 -05:00
David Harris
808f60afbb Started DV Test Plan 2023-04-17 10:18:06 -07:00
David Harris
64fe318cb0 merged coverage exclusions 2023-04-17 10:17:48 -07:00
Ross Thompson
30d017c258 Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster. 2023-04-17 12:16:31 -05:00
Ross Thompson
fe692dacce Finally got the arty a7 to build. 2023-04-17 11:54:22 -05:00
Ross Thompson
4ad33d7acc OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :( 2023-04-17 11:10:19 -05:00
David Harris
bd32b3889f Merge pull request #248 from dherreravicioso/main 
Added test coverage for reads to HPM counters and coverage exclusions
 2023-04-16 18:18:31 -07:00
Ross Thompson
5591b447d6 Fixed more issues with arty a7 constarints. 2023-04-16 13:25:02 -05:00
Diego Herrera Vicioso
16fd17be39 Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc 2023-04-15 23:13:39 -07:00