144 Commits

Author	SHA1	Message	Date
David Harris	21c1e58829	Partitioned privilege mode fsm into new module	2022-05-12 16:16:42 +00:00
David Harris	e2dea3bb89	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
mmasserfrye	52b0e7d567	filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv	2022-05-12 07:22:06 +00:00
David Harris	a8c9f504fa	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	91472eb948	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
David Harris	66424a8246	SFENCE.VMA should be illegal in user mode	2022-05-05 15:15:02 +00:00
David Harris	c100c9893b	wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts	2022-05-05 14:37:21 +00:00
David Harris	94459ade3d	Changed WFI to stall pipeline in memory stage	2022-05-05 02:03:44 +00:00
Kip Macsai-Goren	0f70e48b6b	updated makefrag and tests.vh to reflect removed tests, new names	2022-05-04 21:20:25 +00:00
Kip Macsai-Goren	e557e420b6	added missing SIE test	2022-04-29 19:54:29 +00:00
Kip Macsai-Goren	5df381e26f	renamed PIE-stack tests to status-mie for clarity	2022-04-29 18:30:39 +00:00
Kip Macsai-Goren	c3ffcd0e95	removed old unused tests from wally arch tests	2022-04-28 18:14:08 +00:00
Kip Macsai-Goren	0e5cc40360	added 32 bit versions of new tests. all but timeout wait pass regression	2022-04-28 18:14:07 +00:00
Skylar Litz	970f6c4222	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-27 10:50:19 -07:00
Skylar Litz	594db170de	fix AttemptedInstructionCount from ground zero	2022-04-27 10:45:40 -07:00
Kip Macsai-Goren	0f4ca62157	added working tests to test list, updated regression for new configs	2022-04-25 19:18:15 +00:00
Kip Macsai-Goren	7ff85258f0	added new tests to tests.vh, comented out until they pass regression	2022-04-25 18:22:44 +00:00
David Harris	0ede295e88	Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields	2022-04-25 14:49:00 +00:00
Ross Thompson	8fcd4d47b7	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-21 09:52:42 -05:00
Kip Macsai-Goren	cd53163d9a	added new tests to tests.vh	2022-04-20 17:34:40 +00:00
Kip Macsai-Goren	510021af65	added working general trap tests to regression	2022-04-20 06:48:01 +00:00
Ross Thompson	546ef08eb2	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-19 14:09:50 -05:00
Kip Macsai-Goren	64698aa806	Added working trap test to regression, fixed hanfling of some interrupts	2022-04-18 07:22:16 +00:00
Ross Thompson	a99466a487	Fixed bug I introduced by csrc cleanup and changes to ILA.	2022-04-17 21:45:46 -05:00
Ross Thompson	c409bde6ae	fixed no forcing bug in linux testbench.	2022-04-17 17:49:51 -05:00
David Harris	de5b61291f	Experiments with prefix comparator; minor fixes in WFI and testbench warnings	2022-04-17 21:43:12 +00:00
Kip Macsai-Goren	1f9c987efe	added new tests to makefrag and tests.vh	2022-04-17 21:00:36 +00:00
David Harris	a28831b83e	Added WFI to the testbench instruction name decoder	2022-04-14 17:12:11 +00:00
bbracker	fe53dd1683	fix testbench timing bug where interrupt forcing didn't happen soon enough because it was waiting on StallM	2022-04-14 09:23:21 -07:00
bbracker	eb21e34000	fix ReadDataM forcing	2022-04-13 15:32:00 -07:00
Ross Thompson	2e8afd071e	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-13 13:39:47 -05:00
bbracker	735c75af55	change interrupt spoofing to happen at negative clock edges	2022-04-13 04:31:23 -07:00
bbracker	52ed99ca1b	improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS	2022-04-13 03:37:53 -07:00
bbracker	03f1c01f14	whoops forgot to update AttemptedInstructionCount in interrupt spoofing	2022-04-13 00:49:37 -07:00
bbracker	d3e9703c19	change testbench-linux to by default use attempted instruction count for warning/error messages	2022-04-12 21:22:08 -07:00
Ross Thompson	fc173a7954	Missed the force on uart for no tracking.	2022-04-12 19:37:44 -05:00
Ross Thompson	f995ec2a54	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-10 13:41:27 -05:00
Ross Thompson	c3d9eafe60	Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing.	2022-04-10 13:27:54 -05:00
bbracker	aa71fe542d	upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs	2022-04-08 13:45:27 -07:00
bbracker	3b6cb5f0ba	small signs of life on new interrupt spoofing	2022-04-08 12:32:30 -07:00
Ross Thompson	5e4682fb65	Fixed typo in tests.vh	2022-04-07 16:28:28 -05:00
Kip Macsai-Goren	7425c49f58	updated test signature locations	2022-04-06 07:28:38 +00:00
Katherine Parry	20885f4dea	generating all testfloat vectors	2022-04-04 17:17:12 +00:00
Ross Thompson	57eba4355e	Updated the fpga test bench.	2022-04-01 17:14:47 -05:00
bbracker	54b9745a75	big interrupts refactor	2022-03-30 13:22:41 -07:00
Ross Thompson	3ac736e2d5	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-30 11:09:44 -05:00
Ross Thompson	1993069986	Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.	2022-03-30 11:04:15 -05:00
Ross Thompson	fc2b4453ec	rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.	2022-03-29 23:48:19 -05:00
Ross Thompson	de2672231d	Partial fix to allow byte write enables with fpga and still get a preload to work.	2022-03-29 19:12:29 -05:00
Kip Macsai-Goren	b252122d62	fixed arch bge test signature output location after update	2022-03-29 20:45:18 +00:00