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Author SHA1 Message Date
davidharrishmc
5ceb7f1308 Update README.md 2021-10-18 09:52:40 -07:00
James E. Stine
d895fd7ee5 Sanitization some more on mult_cs.sv 2021-10-18 05:24:16 -05:00
James E. Stine
aafa988ca2 Update some on mult_cs and delete DW02_mult.v 2021-10-18 05:06:49 -05:00
James E. Stine
5a1835622c Add hacky hand-made carry/save multiplier - will improve 2021-10-16 10:37:29 -05:00
Katherine Parry
33e5a078bf cvtfp module documented 2021-10-14 15:25:31 -07:00
James E. Stine
6b30adb309 Clean up some signals - beautification onging 2021-10-14 17:12:00 -05:00
Kip Macsai-Goren
ffcf5f5825 Fixed typo in imperas64mmu tests causing PMP tests not to run. 2021-10-14 13:42:24 -07:00
Skylar Litz
395e070917 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-10-13 15:38:32 -07:00
Skylar Litz
d639222519 add StallM signal back to DivStartE control 2021-10-13 15:34:40 -07:00
James E. Stine
eb64a7f0c9 Update to fpdivsqrt to go on posedge as it should. Also an update to 
individual regression test for TestFloat (still needs some tweaking)
 2021-10-13 17:14:42 -05:00
kipmacsaigoren
d5ed6059c7 added outputs from synth run to test mul changes 2021-10-13 12:38:14 -05:00
bbracker
f2cab415b2 gitignore new logs folder 2021-10-12 10:42:13 -07:00
bbracker
886a650da4 change infrastructure to expect only 6.3 million from buildroot 2021-10-12 10:41:15 -07:00
Shreya Sanghai
d783acbbc5 added DESIGN_COMPLIER to forgotten config files 2021-10-12 10:14:04 -07:00
Katherine Parry
09f51871c5 lint warnings fixed 2021-10-12 09:45:02 -07:00
Katherine Parry
4ea56ac68b some fpu lint warnings fixed - still working on it 2021-10-11 18:32:03 -07:00
kipmacsaigoren
e28d8892ad added historical outputs folder for synth runs 2021-10-11 19:52:52 -05:00
Shreya Sanghai
51185478df made redunantmul generate DW02_multp for synopsys sythnesis 2021-10-11 11:54:39 -07:00
Shreya Sanghai
295a3c7af2 actually added redundant mul 2021-10-11 11:29:13 -07:00
David Harris
f9b37c3ce1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-11 11:21:39 -07:00
David Harris
062fbfb610 Extended lint to check rv32/64g (including fpu. Not clean yet. 2021-10-11 11:20:42 -07:00
Shreya Sanghai
324230e2f9 added redundant multiplier 2021-10-11 11:20:12 -07:00
David Harris
fc39f77cba Starting to optimize multiplier 2021-10-11 11:06:07 -07:00
davidharrishmc
66adcaa9f5 Update README.md 2021-10-11 08:50:44 -07:00
David Harris
f08cb71b87 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-11 08:14:38 -07:00
David Harris
8a64675b02 intdiv cleanup 2021-10-11 08:14:21 -07:00
davidharrishmc
5492178419 Update README.md 2021-10-11 08:13:15 -07:00
David Harris
a8ce4568aa Divider FSM simplification 2021-10-10 22:24:14 -07:00
David Harris
a077735ecc Major reorganization of regression and simulation and testbenches 2021-10-10 15:07:51 -07:00
James E. Stine
11cf3d97c5 Update to missing vectors :P and also run_all script. Also made all scripts .sh as technically run using SH 2021-10-10 15:44:01 -05:00
bbracker
50e5b0a8f4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 13:12:44 -07:00
bbracker
efe9f5d857 make regression expect what buildroot is actually able to reach 2021-10-10 13:12:36 -07:00
David Harris
266c706804 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:26:15 -07:00
David Harris
77f1ae54d8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 12:25:11 -07:00
bbracker
8eff03bf1a simplify flopenrc's that didn't actually need to be flopenrc's 2021-10-10 12:25:05 -07:00
David Harris
93e6ec96a7 Divider cleanup 2021-10-10 12:24:44 -07:00
David Harris
6d2d93deeb Simplifying divider FSM 2021-10-10 12:21:43 -07:00
David Harris
2d09994a91 Simplifying divider FSM 2021-10-10 12:21:36 -07:00
David Harris
644af40855 Moved & ~StallM from FSM into DivStartE 2021-10-10 11:49:32 -07:00
David Harris
e93014d6d8 Moved divide iteration register names to M stage 2021-10-10 11:30:53 -07:00
David Harris
e8d013b106 Simplified remainder for divide by 0 2021-10-10 11:20:07 -07:00
David Harris
94fd682cdc divider control signal simplificaiton 2021-10-10 10:55:02 -07:00
David Harris
bfe8bf3855 Removed negedge flops from divider 2021-10-10 10:41:13 -07:00
bbracker
179223bef0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-10 10:10:06 -07:00
bbracker
5a987cf0ca use correct string formatting function 2021-10-10 10:09:59 -07:00
David Harris
99fd79c20b Simplified divider sign handling 2021-10-10 08:35:26 -07:00
David Harris
eaa8be14b9 renamed DivStart 2021-10-10 08:32:04 -07:00
David Harris
5cb30164d4 renamed DivSigned 2021-10-10 08:30:19 -07:00
Katherine Parry
44b023ace1 FMA matches diagram and lint warnings fixed 2021-10-09 17:38:10 -07:00
bbracker
54e0e8eb5b make testbench-linux halt on some discrepancies with QEMUw 2021-10-09 17:22:30 -07:00