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Configurable RISC-V Processor
1,746 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
2d09994a91
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David Harris 2d09994a91 Simplifying divider FSM
2021-10-10 12:21:36 -07:00
riscv-coremark Made a backup folder accessible to everyone for 3 portme directories that would not be preserved in the case of a clean coremark installation. 2021-08-12 05:23:04 -04:00
testsBP FPGA test bench and test program. 2021-09-12 20:41:54 -05:00
wally-pipelined Simplifying divider FSM 2021-10-10 12:21:36 -07:00
.gitattributes
.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor