Update README.md

This commit is contained in:
davidharrishmc 2021-10-11 08:13:15 -07:00 committed by GitHub
parent a8ce4568aa
commit 5492178419

View File

@ -1,2 +1,7 @@
# riscv-wally
Configurable RISC-V Processor
Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs. It is written in SystemVerilog. It passes the RISC-V Arch Tests and Imperas tests. As of October 2021, it boots the first 10 million instructions of Buildroot Linux.