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Configurable RISC-V Processor
1,751 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
54e0e8eb5b
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bbracker 54e0e8eb5b make testbench-linux halt on some discrepancies with QEMUw
2021-10-09 17:22:30 -07:00
riscv-coremark Made a backup folder accessible to everyone for 3 portme directories that would not be preserved in the case of a clean coremark installation. 2021-08-12 05:23:04 -04:00
testsBP FPGA test bench and test program. 2021-09-12 20:41:54 -05:00
wally-pipelined make testbench-linux halt on some discrepancies with QEMUw 2021-10-09 17:22:30 -07:00
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.gitmodules Added git things to make it all a little nicer and synthesis work. 2021-09-15 12:15:53 -05:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor