David Harris
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94201e993f
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Merge pull request #481 from ross144/main
Fixed the BTB logger so sim_bp correctly reports BTB performance
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2023-11-15 17:45:38 -08:00 |
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Rose Thompson
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9a90c15f37
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Extended SeparateBranch to support both just branches and all control flow instructions.
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2023-11-15 16:36:49 -06:00 |
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David Harris
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cfaeeae25a
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Added cmoz support to imperas.ic and adjusted imperas testbench to no longer need FPGA parameter
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2023-11-15 08:15:01 -08:00 |
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Rose Thompson
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feb45b9b59
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Patched up linux imperas testbench.
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2023-11-14 14:20:13 -06:00 |
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Rose Thompson
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fdb75203cb
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Added cbop to to rv32gc.
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2023-11-14 10:55:22 -06:00 |
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Rose Thompson
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95fc5f4a1c
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Towards removing the FPGA config file.
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2023-11-13 17:20:26 -06:00 |
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David Harris
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426aabbc1a
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Imperas commenting
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2023-11-10 08:26:32 -08:00 |
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David Harris
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7e00581187
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Add Svadu support and SPI to imperas configuration
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2023-11-10 06:27:25 -08:00 |
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David Harris
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625652b9ca
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Reporting stall path in synthesis script, support Zcb in Imperas
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2023-11-09 06:59:29 -08:00 |
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David Harris
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2b183020d5
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Fixed bit manpulation on imperas config
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2023-11-06 14:11:01 -08:00 |
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David Harris
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9c4a7866b8
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Fixed Svnapot_page_mask for imperas.ic
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2023-11-05 06:51:01 -08:00 |
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David Harris
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568aa3c4a6
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Verilator improvements
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2023-11-04 03:21:07 -07:00 |
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naichewa
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fefb5adb8f
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code review harris
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2023-10-31 12:27:41 -07:00 |
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naichewa
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7dd3f24d6c
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Merge branch 'main' into spi
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2023-10-30 17:01:41 -07:00 |
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naichewa
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2330f4ee63
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hardware interlock
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2023-10-30 17:00:20 -07:00 |
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Rose Thompson
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bd04ffc0c9
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Fixed bug in bpred-sim.py for btb and class size sweep.
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2023-10-24 10:29:02 -05:00 |
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Rose Thompson
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ea403e02ff
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Updated bpred-sim.py to take command line options to select between sweeping direction, target, class, or ras prediction.
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2023-10-23 16:09:40 -05:00 |
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David Harris
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b76c371e45
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Config file cleanup
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2023-10-18 05:38:36 -07:00 |
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David Harris
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fab9fbd7f1
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Merged testbench
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2023-10-16 13:52:24 -07:00 |
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David Harris
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1a6e57f8c0
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Renamed wally-config to config in many comments
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2023-10-16 13:49:09 -07:00 |
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David Harris
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ac4216b43d
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Incorporated new AMO tests from riscv-arch-test
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2023-10-16 10:25:45 -07:00 |
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David Harris
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434d6b2c5c
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minfo test working again with mconfigptr for RV64
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2023-10-15 06:41:52 -07:00 |
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Rose Thompson
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8f2ca2ae15
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Added missing files.
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2023-10-13 15:10:58 -05:00 |
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eroom1966
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d690708194
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add in new .sv file
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2023-10-06 13:47:05 +01:00 |
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Lee Moore
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0a0d6dd25e
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Merge branch 'openhwgroup:main' into main
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2023-10-06 11:46:45 +01:00 |
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Ross Thompson
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3bbcfade93
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Completed branch predictor benchmarking.
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2023-09-27 13:56:51 -05:00 |
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Ross Thompson
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f863cbf366
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Actually fixed non-power of 2 issue with RAS.
Added RAS swapping to branch predictor scripts and configurations.
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2023-09-27 12:25:05 -05:00 |
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eroom1966
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381cfdcb4b
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bring upto date with latest IDV
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2023-09-21 11:29:31 +01:00 |
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Ross Thompson
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60ddbe31f8
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Updated the branch predictor simulator's parseHPMC.py results.
In a future commit I will update the branch predictor simulator with the fix for the gshare and then update the commit pointing their repo.
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2023-09-18 16:59:20 -05:00 |
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Ross Thompson
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95c653e7df
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Fixes the bpred-sim.py to support command line parameterization of the branch predictor while using the new parameterization. This is definitely a hack, but I don't see a better way.
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2023-09-15 14:05:26 -05:00 |
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Ross Thompson
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9ff3642c6c
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-09-05 11:12:00 -05:00 |
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Ross Thompson
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de54b5c4d8
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Updated wavefile
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2023-09-05 11:11:56 -05:00 |
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David Harris
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9747d122d2
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tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker
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2023-09-02 12:56:36 -07:00 |
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David Harris
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1642ad2bad
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Improved NAPOT test coverage
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2023-08-30 21:04:36 -07:00 |
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Ross Thompson
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310b700550
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Have a working 32 bit cbom test!
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2023-08-21 13:46:09 -05:00 |
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Ross Thompson
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a89a1e675c
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Merge branch 'boot' into mergeBoot
Merges Jacob's new sdc controller into wally.
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2023-07-21 17:43:45 -05:00 |
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Ross Thompson
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af0e33209f
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Removed QEMU from configurations.
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2023-07-19 10:23:55 -05:00 |
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Ross Thompson
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9533dee300
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Got xcelium running wally, but it fails to actually preload the memories.
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2023-07-12 13:56:57 -05:00 |
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Ross Thompson
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625192d9a4
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Merge branch 'main' of github.com:ross144/cvw into main
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2023-07-11 15:08:26 -05:00 |
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Ross Thompson
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27f6f00402
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Changes for xcelium.
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2023-07-07 18:22:28 -05:00 |
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Ross Thompson
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235546fa06
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Merge branch 'main' of github.com:ross144/cvw
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2023-07-07 13:25:00 -05:00 |
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James E. Stine
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67fdeae9c9
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Add reset to wave window
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2023-06-29 08:47:16 -05:00 |
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Ross Thompson
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c6a55c446a
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-27 11:04:27 -05:00 |
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Ross Thompson
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cc5d8fbf06
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Updates for fpga.
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2023-06-27 11:04:20 -05:00 |
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James E. Stine
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dd6b12c6dc
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Add signals for ResMatch & CheckNow to sim window that are related to TestFloat operation
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2023-06-26 10:15:46 -05:00 |
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James E. Stine
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0b7b28c2f0
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For some reason this was modified - I probably made a mistake - put back vsim
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2023-06-22 15:26:22 -05:00 |
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James E. Stine
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1f63e6d483
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Remove path for cvw.sv so its found
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2023-06-22 15:25:56 -05:00 |
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James E. Stine
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66643eb78e
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Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file
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2023-06-20 17:26:54 -05:00 |
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eroom1966
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5f358d1af7
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add changes for latest IDV file layout
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2023-06-16 16:43:53 +01:00 |
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Ross Thompson
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4428babda9
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-15 15:38:38 -05:00 |
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