cvw/sim
2023-09-27 13:56:51 -05:00
..
bp-results Completed branch predictor benchmarking. 2023-09-27 13:56:51 -05:00
slack-notifier Renamed regression to sim 2023-02-02 14:48:23 -08:00
wave-dos Renamed regression to sim 2023-02-02 14:48:23 -08:00
bpred-sim.py Actually fixed non-power of 2 issue with RAS. 2023-09-27 12:25:05 -05:00
buildrootBugFinder.py Renamed wally-piplined.do to wally.do 2023-02-04 04:38:41 -08:00
coverage tlbNAPOT hangs due to PBMT making instruction memory uncacheable, and spill logic not working there. Fixed TLBLRU to update recently used on TLBHit rather than CAMHit. Moved coverage exclusions to proper line in pmachecker 2023-09-02 12:56:36 -07:00
coverage-exclusions-rv64gc.do Exclusions for decoders with new parameterization 2023-05-30 01:04:39 -07:00
FPbuild.txt Update sim-testfloat to fix errors due to bad config element. I am not sure of the reasoning, but the specific path to the testvector was not getting inserted in Questa. This modification also adds features to test individualized tests (.e.g, binary16 only) -- documentation is added in the FPbuild.txt file 2023-06-20 17:26:54 -05:00
fpga-wave.do Renamed regression to sim 2023-02-02 14:48:23 -08:00
GetLineNum.do track GetLinenum.do (tcl procedure to find line numbers to exclude) 2023-04-12 15:58:38 -07:00
imperas.ic add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
lint-wally Merge branch 'boot' into mergeBoot 2023-07-21 17:43:45 -05:00
linux-wave.do Modified the imperas linux scripts so they run without reporting hundreds of gigabytes of data. 2023-04-26 17:29:57 -05:00
make-tests.sh Renamed regression to sim 2023-02-02 14:48:23 -08:00
Makefile Eliminated merging non-existent coverage 2023-05-30 00:38:30 -07:00
makefile-memfile Renamed regression to sim 2023-02-02 14:48:23 -08:00
regression-wally Removed unnecessary imperas tests from coverage 2023-05-23 15:43:11 -07:00
run-imperas-linux.sh Revert "Update for new layout of ImperasDV files" 2023-06-13 04:17:56 -07:00
run-imperasdv-tests.bash Revert "Update for new layout of ImperasDV files" 2023-06-13 04:17:56 -07:00
rv64gc_CacheSim.py Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
sim-buildroot Renamed wally-piplined.do to wally.do 2023-02-04 04:38:41 -08:00
sim-buildroot-batch Renamed wally-piplined.do to wally.do 2023-02-04 04:38:41 -08:00
sim-imperas Revert "Update for new layout of ImperasDV files" 2023-06-13 04:17:56 -07:00
sim-testfloat Renamed regression to sim 2023-02-02 14:48:23 -08:00
sim-testfloat-batch For some reason this was modified - I probably made a mistake - put back vsim 2023-06-22 15:26:22 -05:00
sim-wally Renamed wally-piplined.do to wally.do 2023-02-04 04:38:41 -08:00
sim-wally-batch Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-06-15 15:38:38 -05:00
test Renamed regression to sim 2023-02-02 14:48:23 -08:00
testfloat.do Remove path for cvw.sv so its found 2023-06-22 15:25:56 -05:00
verilate Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. 2023-05-31 16:51:00 -05:00
wally-batch.do Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this. 2023-06-14 09:44:52 -07:00
wally-imperas-cov.do add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
wally-imperas-no-idv.do add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
wally-imperas.do Removed QEMU from configurations. 2023-07-19 10:23:55 -05:00
wally-linux-imperas.do add changes for latest IDV file layout 2023-06-16 16:43:53 +01:00
wally.do Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this. 2023-06-14 09:44:52 -07:00
wally.xrun Got xcelium running wally, but it fails to actually preload the memories. 2023-07-12 13:56:57 -05:00
wave-all.do Renamed regression to sim 2023-02-02 14:48:23 -08:00
wave-fpu.do Add reset to wave window 2023-06-29 08:47:16 -05:00
wave.do Completed branch predictor benchmarking. 2023-09-27 13:56:51 -05:00