David Harris
f9202187ba
Removed comment about nonexistent possible bug
2022-11-14 09:52:21 -08:00
Ross Thompson
13e6f7d80b
Changed names of cache signals.
2022-11-13 21:36:12 -06:00
Ross Thompson
788ae5fb18
Updated wave file.
2022-11-13 21:34:45 -06:00
cturek
abaa33b92a
Added majority of combinational logic
2022-11-14 00:06:38 +00:00
cturek
6740d77b63
Added Quotient/Remainder calcs to normal termination
2022-11-13 23:44:34 +00:00
cturek
12e3646153
Added flops for n and m, added B=0 signal
2022-11-13 23:02:43 +00:00
cturek
f10700e666
Added A<B signal to fdivsqrt, started postprocessing merge
2022-11-13 22:40:26 +00:00
Ross Thompson
9d7ba19fe1
Changed IMWriteDataM to IHWriteDataM.
2022-11-13 12:27:48 -06:00
Ross Thompson
421c6f9c48
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
...
hazard was not a straight forward merge. I changed the way the LSU and IFU generate IFUStallF and LSUStallM. They need to be suppressed by TrapM now.
2022-11-13 12:25:22 -06:00
David Harris
84c4558641
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-13 04:23:26 -08:00
David Harris
879e62912b
HPTW cleanup
2022-11-13 04:23:23 -08:00
David Harris
2ebdfa3f68
Comments about division hazards
2022-11-13 04:17:37 -08:00
Ross Thompson
cc80f1f7b2
Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s).
...
Increased CPU clock speed from 30 Mhz to 35 Mhz.
2022-11-11 15:33:03 -06:00
Ross Thompson
54544ae251
Moved all remaining bus logic from the LSU into ahbcacheinterface.
2022-11-11 14:30:32 -06:00
cturek
4a8661649c
Added integer step counter to fsm
2022-11-11 00:23:25 +00:00
Ross Thompson
c028306ba3
Fixed name change in hptw.
2022-11-10 16:13:31 -06:00
Ross Thompson
d912981ec9
Wavefile update.
2022-11-10 15:48:06 -06:00
Ross Thompson
40367eaf45
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-10 15:46:25 -06:00
Ross Thompson
8658a25218
Renamed Word to Beat for ahbcacheinterface.
2022-11-09 17:52:50 -06:00
Ross Thompson
028e2b0f91
Renamed CACHE_EVICT to CACHE_WRITEBACK.
2022-11-09 17:43:06 -06:00
Ross Thompson
30b2bd263c
Updates to fpga constraints.
2022-11-09 13:52:36 -06:00
cturek
9d30a832c3
Reoredered tests for arch32m
2022-11-09 18:42:00 +00:00
cturek
b723e16893
Fixed asign and bsign
2022-11-09 18:41:26 +00:00
Ross Thompson
be8e0eee1b
Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU).
...
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS.
FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to
not stall W if we get a trap.
2022-11-07 15:50:55 -06:00
David Harris
f7b94c12fc
Moved lsuvirtmem muxes into hptw
2022-11-07 11:13:34 -08:00
Ross Thompson
5c49cc4dd0
Fixed bug with fpga makefile.
2022-11-07 09:20:05 -06:00
Ross Thompson
d4f4950d2c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-07 09:10:51 -06:00
Kip Macsai-Goren
21e045eb7d
added potential fix to overrun error and fifo interrupt error. test passes
2022-11-06 22:01:02 -08:00
cturek
d571b5f9a5
propagated otfc swap to Rad2 and 4 qslc
2022-11-06 23:32:38 +00:00
Ross Thompson
e7d24609cd
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-06 17:22:25 -06:00
cturek
54f09f3616
Added conditional OTFC swap for simplified int postprocessing
2022-11-06 23:09:09 +00:00
cturek
c3e635c788
Finished Int Preprocessinggit add ../src/fpu/fdivsqrt/fdivsqrtpreproc.sv
2022-11-06 22:40:21 +00:00
cturek
a49ea2a16d
Added n and rightshiftx
2022-11-06 22:31:48 +00:00
cturek
350d4d254f
p calculation
2022-11-06 22:24:21 +00:00
cturek
83051a5351
Changed lzc names, started int/fp size merge in preproc
2022-11-06 22:21:35 +00:00
cturek
2cbe2fd70b
Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.
2022-11-06 22:08:18 +00:00
cturek
6bc4c1318e
Added new macros for int div preprocessing, added p, n, and rightshiftx logic
2022-11-06 21:53:48 +00:00
Kip Macsai-Goren
90ef371abc
fixed fifo timout handling. error now in data ready interrupt
2022-11-05 13:34:24 -07:00
David Harris
53a88fec8f
Reorder embench tests to prevent crash
2022-11-04 15:21:51 -07:00
David Harris
60cfa0d69c
HPTW cleanup
2022-11-04 15:21:09 -07:00
Ross Thompson
44ee31a7f6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-04 13:30:08 -05:00
Kip Macsai-Goren
c06da6e6fe
fixed broken instructions so make works.
2022-11-03 23:06:20 +00:00
Ross Thompson
65feca8bed
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-03 17:48:35 -05:00
Ross Thompson
f1eb20ef4d
Updated to put dtb into the rodata segment for our linker script.
2022-11-03 17:48:20 -05:00
cturek
06a9305766
renamed remOp to RemOp
2022-11-03 22:37:25 +00:00
Ross Thompson
1d7002e5c5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-11-03 17:36:04 -05:00
Ross Thompson
ccce0df535
Potentially a valid zero stage boot loader based on cva6.
2022-11-03 17:35:57 -05:00
cturek
e37f564e84
Added rem/div operation to postprocessor
2022-11-02 17:49:40 +00:00
Ross Thompson
44171c342d
Reduced complexity of logic supressing cache operations.
2022-11-01 15:23:24 -05:00
cturek
e8d7607e87
Added buffered signals for int/fp
2022-10-28 21:47:24 +00:00
