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686 Commits

Author SHA1 Message Date
David Harris
2d8ccbd4ea More trap/csr simplification 2022-05-12 22:00:23 +00:00
David Harris
417e36bff5 More trap/csr simplification 2022-05-12 21:55:50 +00:00
David Harris
ca6b7716e2 Simplifying trap/csr interface 2022-05-12 21:50:15 +00:00
David Harris
56c154f2e7 Simplified MTVAL logic 2022-05-12 21:36:13 +00:00
David Harris
730bcac6ba Partitioned privileged pipeline registers into module 2022-05-12 20:45:45 +00:00
David Harris
c5868b81e4 privileged cleanup 2022-05-12 20:21:33 +00:00
mmasserfrye
517e44746e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 20:20:40 +00:00
mmasserfrye
2675c217e0 cleaned lint for ppa.sv 2022-05-12 20:20:05 +00:00
David Harris
5537c33196 Formatting cleanup 2022-05-12 18:37:47 +00:00
mmasserfrye
57a69d0f67 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 18:08:20 +00:00
mmasserfrye
30a1ba7bcf renamed madzscript, modified ppa.sv alu and shifter 2022-05-12 18:05:02 +00:00
David Harris
449472ba58 Moved Breakpoint and Ecall fault logic into privdec 2022-05-12 16:45:53 +00:00
David Harris
9f8dca5190 Moved TLB Flush logic into privdec 2022-05-12 16:41:52 +00:00
David Harris
1d01bc98a4 Moved WFI timeout into privdec 2022-05-12 16:22:39 +00:00
David Harris
21c1e58829 Partitioned privilege mode fsm into new module 2022-05-12 16:16:42 +00:00
David Harris
61199ccd13 More signal cleanup 2022-05-12 15:39:44 +00:00
David Harris
4c5e361b00 More unused signal cleanup 2022-05-12 15:26:08 +00:00
David Harris
5acb526375 More unused signal cleanup 2022-05-12 15:21:09 +00:00
David Harris
7e764fbda1 More unused signal cleanup 2022-05-12 15:15:30 +00:00
David Harris
e2dea3bb89 Removed more unused signals, simplified csri state 2022-05-12 15:10:10 +00:00
David Harris
fb725a9e0a Clean up unused signals 2022-05-12 14:49:58 +00:00
David Harris
8372bc86a7 Removing unused signals 2022-05-12 14:36:15 +00:00
David Harris
15659b05e4 Simplifed mstatus.TSR handling 2022-05-12 14:09:52 +00:00
David Harris
877c4eefd1 Fixed typo in csrm 2022-05-12 06:55:39 -07:00
mmasserfrye
cf900cf44d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-12 07:24:04 +00:00
mmasserfrye
52b0e7d567 filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
David Harris
32f8841f79 Added MCONFIGPTR CSR hardwired to 0 2022-05-12 04:31:45 +00:00
David Harris
c738c130de merged ppa.sv 2022-05-11 18:14:16 +00:00
David Harris
e37d262e4c PPA script progress 2022-05-11 18:11:51 +00:00
mmasserfrye
70fe1184db ed 
modified ppa.sv
 2022-05-11 16:22:12 +00:00
David Harris
a8c9f504fa Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt 2022-05-11 15:08:33 +00:00
David Harris
91472eb948 Removed M suffix from interrupts because they are generated asynchronously to pipeline 2022-05-11 14:41:55 +00:00
David Harris
91b786c58d Updated PPA experiment 2022-05-10 23:09:42 +00:00
David Harris
d53e4b1b1f Initial PPA study 2022-05-10 20:48:47 +00:00
David Harris
b869190161 endian swapper 2022-05-08 06:51:50 +00:00
David Harris
8066ba45e8 Preliminary support for big endian modes. Regression passes but no big endian tests written yet. 2022-05-08 06:46:35 +00:00
David Harris
2792d77e4e Fixed bug in delegated interrupts not being taken 2022-05-08 04:50:27 +00:00
David Harris
2cdd49c7d2 WFI terminates when an interrupt is pending even if interrupts are globally disabled 2022-05-08 04:30:46 +00:00
David Harris
7024293a59 Zero'd wfiM when ZICSR not supported to fix hang in E tests 2022-05-05 15:32:13 +00:00
David Harris
66424a8246 SFENCE.VMA should be illegal in user mode 2022-05-05 15:15:02 +00:00
David Harris
866540580a SFENCE.VMA should be illegal in user mode 2022-05-05 14:59:52 +00:00
David Harris
c100c9893b wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
David Harris
94459ade3d Changed WFI to stall pipeline in memory stage 2022-05-05 02:03:44 +00:00
Kip Macsai-Goren
25ad39939f put privileged tests back into rv32/64gc 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
0f70e48b6b updated makefrag and tests.vh to reflect removed tests, new names 2022-05-04 21:20:25 +00:00
David Harris
8eee0c0ca3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-05-03 18:32:04 +00:00
David Harris
554c2b3550 Illegal instruction fault when running FPU instruction with STATUS_FS = 0 2022-05-03 18:32:01 +00:00
David Harris
cb1a7d54a4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-05-03 08:53:35 -07:00
David Harris
4fbf78e049 clean up sram1p1rw; still doesn't work on Modelsim 2022.1 2022-05-03 08:31:54 -07:00
David Harris
9c4de0e9c1 FPU generates illegal instruction if MSTATUS.FS = 00 2022-05-03 11:56:31 +00:00
David Harris
dee32f70bf Switched to behavioral comparator for best PPA 2022-05-03 11:00:39 +00:00
David Harris
bc123b5564 Comparator experiments 2022-05-03 10:54:30 +00:00
David Harris
7e3f75a35d Formatting cache.sv 2022-05-03 10:53:20 +00:00
David Harris
bc132c3e20 sram1p1rw extra bits are complaining on Tera and VLSI; roll back to two always blocks to fix on Tera 2022-05-03 03:50:41 -07:00
David Harris
3f2ec0499f Rewriting sram1p1rw to combine CacheData into a single always_ff. Extra bits are still giving warning on VLSI that don't make sense. 2022-05-03 03:45:41 -07:00
David Harris
7268ff1fd4 Changed loop variable in CLINT because of error only seen on VLSI 2022-05-03 10:10:28 +00:00
Kip Macsai-Goren
e557e420b6 added missing SIE test 2022-04-29 19:54:29 +00:00
Kip Macsai-Goren
5df381e26f renamed PIE-stack tests to status-mie for clarity 2022-04-29 18:30:39 +00:00
Kip Macsai-Goren
c3ffcd0e95 removed old unused tests from wally arch tests 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
3d1e1202f3 set WFI timeout to after 16 bits of counting for all configs 2022-04-28 18:14:08 +00:00
Kip Macsai-Goren
0e5cc40360 added 32 bit versions of new tests. all but timeout wait pass regression 2022-04-28 18:14:07 +00:00
Skylar Litz
970f6c4222 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-27 10:50:19 -07:00
Skylar Litz
594db170de fix AttemptedInstructionCount from ground zero 2022-04-27 10:45:40 -07:00
David Harris
6e8b27de17 Added torture.tv test vectors 2022-04-27 13:08:36 +00:00
David Harris
ffd4713fd1 Checked in torture.tv 2022-04-27 13:06:24 +00:00
David Harris
9042844b38 Cleaned up canonical NaNs and removed denorm outputs in baby_torture.tv 2022-04-26 19:41:30 +00:00
Kip Macsai-Goren
89cce88d33 fixed incorrect configs in regression 2022-04-25 19:28:47 +00:00
Kip Macsai-Goren
0f4ca62157 added working tests to test list, updated regression for new configs 2022-04-25 19:18:15 +00:00
Kip Macsai-Goren
8ad920fcb3 fixed initial value, timing on fs bits changing after floating point instruction 2022-04-25 19:17:29 +00:00
Kip Macsai-Goren
da29193f9b removed atomic, floating point from privileged tests configs 2022-04-25 19:13:15 +00:00
Kip Macsai-Goren
7ff85258f0 added new tests to tests.vh, comented out until they pass regression 2022-04-25 18:22:44 +00:00
Kip Macsai-Goren
7fe33b2147 Lowered WFI timeout wait time for privileged configs 2022-04-25 17:47:10 +00:00
David Harris
cf1fde62fb Restored MPRV behavior per spec 2022-04-25 14:52:18 +00:00
David Harris
0ede295e88 Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields 2022-04-25 14:49:00 +00:00
David Harris
851d5e8c5e Added MTINST hardwired to 0, and added timeout of U-mode WFI 2022-04-24 20:00:02 +00:00
David Harris
16ad1e0cab Fixed InstrMisalignedFaultM mtval 2022-04-24 17:31:30 +00:00
David Harris
f1ddbb169c Improved priority order and mtval of traps to match spec 2022-04-24 17:24:45 +00:00
David Harris
03f84bf11c Extended sim time to fully boot Linux. Added comments to hazard unit 2022-04-24 13:51:00 +00:00
Kip Macsai-Goren
7bc6943527 Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address) 2022-04-22 22:46:11 +00:00
bbracker
5e76c83309 deprecate unused LINUX_FIX_READ macro 2022-04-21 19:14:47 -07:00
bbracker
afc38abe08 change how tristate I/O is spoofed in GPIO loopback test 2022-04-21 10:31:16 -07:00
Ross Thompson
8fcd4d47b7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-21 09:52:42 -05:00
Ross Thompson
165a36acac Modified wally-pipelined.do for no trace linux sim. 2022-04-21 09:52:33 -05:00
David Harris
5c607f2b6b Simplified profile for UART boot; added warnings on UART Rx errors 2022-04-21 04:54:45 +00:00
Kip Macsai-Goren
cd53163d9a added new tests to tests.vh 2022-04-20 17:34:40 +00:00
Kip Macsai-Goren
080963c381 fixed rv32ia to support clint and GPIO for priv tests 2022-04-20 17:31:34 +00:00
Kip Macsai-Goren
510021af65 added working general trap tests to regression 2022-04-20 06:48:01 +00:00
Ross Thompson
546ef08eb2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-19 14:09:50 -05:00
David Harris
1f7a95637a Added baby torture tests 2022-04-19 15:13:06 +00:00
David Harris
a8ad7be246 Fixed WFI decoding in IFU 2022-04-18 19:02:08 +00:00
Kip Macsai-Goren
1ba328324b Added GPIO loopback to let outputs cause interrupts 2022-04-18 07:22:49 +00:00
Kip Macsai-Goren
64698aa806 Added working trap test to regression, fixed hanfling of some interrupts 2022-04-18 07:22:16 +00:00
Shreya Sanghai
fd3920b217 replaced k with bpred size 2022-04-18 04:21:03 +00:00
Shreya Sanghai
c3164f0ce1 added bpred size to wally config 2022-04-18 04:21:03 +00:00
David Harris
462158ea92 LSU name cleanup 2022-04-18 03:18:38 +00:00
Ross Thompson
a99466a487 Fixed bug I introduced by csrc cleanup and changes to ILA. 2022-04-17 21:45:46 -05:00
David Harris
4a7effaf9e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-18 01:30:11 +00:00
David Harris
2882460c94 Renamed FinalAMOWriteDataM to AMOWriteDataM 2022-04-18 01:30:03 +00:00
David Harris
861fbd698b Run 4M instructions in buildroot test to get through kernel & VirtMem startup 2022-04-18 01:29:38 +00:00
Ross Thompson
c045e3afd8 Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00