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4,241 Commits 4 Branches 2 Tags 53 MiB
1e7bbe1a87
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107 Commits

Author SHA1 Message Date
Jacob Pease
1e7bbe1a87 Fixed rxfifotimeout restarting for every new character, even when already high. 2022-09-19 18:00:30 -05:00
Ross Thompson
68a200d728 Added generate around the longer latency version of the ram_ahb.sv 2022-09-06 09:21:03 -05:00
Ross Thompson
2554f96662 Cleaned up hacks to ram. 2022-09-04 14:52:40 -05:00
Ross Thompson
c87268baf1 Modified ram_ahb to work with different latencies. 2022-09-04 14:46:15 -05:00
Ross Thompson
f9daa7f6b9 Progress towards fixing the select HREADY muxing in uncore. 2022-09-04 13:07:49 -05:00
Ross Thompson
4d60d9a840 Fixed up FPGA constraints. 
Added back in the fpga boot rom preload.
 2022-09-02 13:54:35 -05:00
Ross Thompson
122c88ee46 Created two new pma regions for dtim and irom. 2022-08-28 13:50:50 -05:00
Ross Thompson
5e63af5887 Reordered the adrdecs. 2022-08-28 13:38:57 -05:00
David Harris
f2517f8290 Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus. 2022-08-27 20:31:09 -07:00
David Harris
f0b4f69b65 Added IROM and DTIM decoding to adrdecs 2022-08-26 20:45:43 -07:00
David Harris
902d2067ba Removed delayed AHB signals from top level 2022-08-25 15:34:14 -07:00
David Harris
302a7fa294 Extended HADDR to PA_BITS 2022-08-25 13:11:36 -07:00
Ross Thompson
ad485fe591 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:03:34 -05:00
Ross Thompson
701324eeb8 Updated ila signals. 
Improve fpga wave config.
added back in the fpga preload.
 2022-08-25 09:03:29 -05:00
David Harris
562be633ab Stripped write capaibilty out of rom_ahb 2022-08-24 17:23:08 -07:00
David Harris
a131e1f17a Added ROM module and moved memories into generic/mem 2022-08-24 17:03:22 -07:00
David Harris
6785644fb8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-24 16:30:28 -07:00
David Harris
b21b91234b Ram cleanup 2022-08-24 16:30:25 -07:00
Ross Thompson
769af32f2a Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
Ross Thompson
fc22e807e2 Merged testbench-fpga into testbench. 
Modified SDC to simplify LimitTimers.  LimitTimers needs to be 0 for implmementation and 1 for simulation.
 2022-08-24 17:52:25 -05:00
David Harris
93d7d7179e Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
slmnemo
ca4511b6dc Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
David Harris
d22587090b Reset MSR on read 2022-07-22 04:29:27 +00:00
slmnemo
3d2c6683d8 Fixed UART bug related to parity and MSR/LSR 2022-07-21 20:35:46 -07:00
David Harris
622773343f restored intPending logic to be sticky for PLIC 2022-07-16 17:43:31 -07:00
David Harris
5ae88dbef0 Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc 2022-07-08 09:09:02 +00:00
David Harris
96cc66d151 Adjusting byte writes to RAM 2022-07-08 08:45:21 +00:00
David Harris
234175f236 Removed unused swbytemask from CLINT 2022-07-08 08:43:24 +00:00
David Harris
76302a8599 PLIC and UART passing tests on APB 2022-07-06 13:26:14 +00:00
David Harris
72e216d053 APB CLINT passing regression 2022-07-05 15:51:35 +00:00
David Harris
5f5ad77d4a Modified uncore to use AHB bridge to GPIO 2022-07-05 05:02:21 +00:00
David Harris
c8ac05ba7b AHB bridge for gpio 2022-07-05 05:01:59 +00:00
David Harris
1a356312b2 Added comments to PLIC about likely bug 2022-07-05 05:00:29 +00:00
David Harris
44216b3967 Fixed typo in clint 2022-06-23 21:27:46 +00:00
David Harris
d969edeb99 Reset mtimecmp in clint 2022-06-23 21:20:55 +00:00
David Harris
802bfd74fb Cleanup on RAM module 2022-06-13 19:37:43 +00:00
David Harris
3c44b5842b Typo in gpio reset 2022-06-13 19:37:05 +00:00
David Harris
09d72a33c5 Fixed XOR logic in GPIO 2022-06-13 19:26:03 +00:00
slmnemo
cc8acd947d Fixed lint error 2022-06-09 17:22:04 -07:00
David Harris
c1a40a15dd New RAM for further testing 2022-06-09 23:50:43 +00:00
David Harris
5612ca7041 qslc_r4a2 generator 2022-06-09 17:26:47 +00:00
David Harris
b53aef33f5 Modified RAM for single-cycle latency 2022-06-08 02:06:00 +00:00
David Harris
cc06fa1c55 Cleaned bram interface 2022-06-08 01:39:44 +00:00
David Harris
f81719337e Added ahbapbbridge and cleaning RAM 2022-06-08 01:31:34 +00:00
Ross Thompson
13f7f48776 Possible plic fix? 2022-05-22 23:47:01 -05:00
Ross Thompson
848abf29b5 Fixed receive fifo ITNR bug. 2022-05-22 10:55:28 -05:00
Ross Thompson
1318f702cf Added more debug signals to uart. 2022-05-21 19:47:40 -05:00
David Harris
a8c9f504fa Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt 2022-05-11 15:08:33 +00:00
David Harris
91472eb948 Removed M suffix from interrupts because they are generated asynchronously to pipeline 2022-05-11 14:41:55 +00:00
David Harris
7268ff1fd4 Changed loop variable in CLINT because of error only seen on VLSI 2022-05-03 10:10:28 +00:00